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| DATA SHEET MOS INTEGRATED CIRCUIT PD17015 4-BIT SINGLE-CHIP MICROCONTROLLER FOR PORTABLE RADIOS The PD17015 is a super low-voltage 4-bit single-chip microcontroller for digital tuning applications. It features a prescaler that can operate at frequencies up to 220 MHz, a PLL synthesizer, and an LCD controller/driver, all configured in one chip. Since, for its CPU, the PD17015 adopts a 17K architecture which allows data memory to be manipulated directly without accumulators, programming efficiency is enhanced. Each instruction is 16 bits (one word) long. Since this microcontroller can operate at low voltages (VDD = 1.8 to 3.6 V), it is ideal for controlling portable, batterypowered units such as portable radios, headphone stereo sets, and radio-cassette players. FEATURES * * * * * 17K architecture Program memory (ROM) Data memory (RAM) General-purpose I/O ports * LCD controller/driver * Clock generator port : General registers : 3K bytes (1528 x 16 bits) : 97 x 4 bits : 12 : 9 segments x 4 commons Minimum required peripheral hardware is built into the chip. * PLL frequency synthesizer and 220-MHz (MAX.) prescaler * Low-voltage operation ORDERING INFORMATION Part number : VDD = 1.8 to 3.6 V (TA = -10 to +50 C) Package 38-pin plastic shrink SOP (300 mil) PD17015GS-xxx-GJG Remark xxx is a ROM code number. The information in this document is subject to change without notice. Document No. U10416EJ1V0DS00 (1st edition) Date Published September 1995 P Printed in Japan Major changes in this revision are indicated by stars (5) in the margins. (c) 1995 PD17015 FUNCTION OVERVIEW Item Program memory (ROM) General-purpose data memory Instruction execution time * 3K bytes (1528 x 16 bits) * 97 x 4 bits * 53.3 s (when 75 kHz crystal is used) * 1 level * I/O * Input only : 2 ports : 3 ports Function 5 Stack levels General-purpose ports 12 * Output only : 7 ports BEEP output LCD controller/driver 1 (3 kHz) * 9 segments, 4 commons * 1/4 duty, 1/2 bias, frame frequency 62.5 Hz, driving voltage 3.0 V (TYP.) Timers 2 channels Basic timer 0 : 125 ms Basic timer 1 : 5 ms 5 Reset * Power-on reset * Reset with the CE pin (by switching the CE pin from low to high) * Power-failure detection function PLL Frequency division frequency method synthesizer Reference frequency Charge pump Phase comparator Supply voltage 2 * Direct division method * Pulse swallow method (VCOL pin (MF mode) : 8 MHz MAX.) (VCOL pin (HF mode) : 55MHz MAX.) (VCOH pin (VHF mode) : 220MHz MAX.) 1, 3, 5, or 25 kHz, selected by software. Error-out output: 1 An unlocked state can be detected by software. * 1.8 to 3.6 V (TA = -10 to +50 C) * 1.9 to 3.6 V (TA = -20 to +50 C) 38-pin plastic shrink SOP (0.65-mm pitches, 300 mil) 5 Package 2 PD17015 BLOCK DIAGRAM P0A0 P0A1 P0A P0A2 P0A3 RF RAM 97 x 4 bits SYSTEM REGISTER LCD0 LCD1 LCD2 LCD3 LCD4 P0B0 P0B1 P0B2 P0B LCD5 LCD Controller/ Driver LCD6 LCD7 LCD8 ALU P0C0 P0C1 P0C P0C2 P0C3 COM0 Instruction Decoder COM1 COM2 COM3 Beep ROM 1528 x 16 bits Voltage Doubler Program Counter 11 bits VLCD0 VLCD1 CAP0 CAP1 EO PLL VCOH VCOL P0OD0/BEEP P0D Basic Timer 0 Basic Timer 1 Stack 1 x 11 bits XIN XOUT OSC CPU Peripheral PLL Voltage Regulator VREG Reset VDD CE GND 3 PD17015 PIN CONFIGURATION (TOP VIEW) 38-pin plastic shrink SOP (300 mil) P0B2 P0C0 P0C1 P0C2 P0C3 P0D0/BEEP P0A0 P0A1 P0A2 P0A3 CE XOUT XIN VDD GND EO VREG VCOH VCOL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 P0B1 P0B0 VLCD0 CAP0 CAP1 VLCD1 COM0 COM1 COM2 COM3 LCD0 LCD1 LCD2 LCD3 LCD4 LCD5 LCD6 LCD7 LCD8 PD17015GS-xxx-GJG BEEP : BEEP output drive voltage P0B0 - P0B2 P0C0 - P0C3 P0D0 VDD VLCD0, VLCD1 VREG XIN, XOUT : Port 0B (input) : Port 0C (output) : Port 0D (output) : Main power supply : LCD power supply : Voltage regulator output for PLL : Crystal connection CAP0, CAP1 : Capacitor connection for LCD CE EO GND P0A0, P0A1 P0A2, P0A3 : Chip enable input : Error out : Ground : Port 0A (I/O) : Port 0A (output) VCOH, VCOL : Local oscillation input COM0 - COM3: LCD common output LCD0 - LCD8 : LCD segment output 4 PD17015 CONTENTS 1. PIN FUNCTIONS ......................................................................................................................... 1.1 1.2 1.3 1.4 PIN FUNCTIONS ............................................................................................................................. EQUIVALENT CIRCUIT OF EACH PIN ......................................................................................... HANDLING UNUSED PINS ............................................................................................................ NOTES ON USE OF THE CE PIN ................................................................................................. 8 8 9 12 13 2. PROGRAM MEMORY (ROM) ..................................................................................................... 2.1 2.2 2.3 2.4 2.5 OUTLINE OF PROGRAM MEMORY ............................................................................................. PROGRAM MEMORY CONFIGURATION ..................................................................................... PROGRAM COUNTER ................................................................................................................... PROGRAM FLOW ........................................................................................................................... NOTES ON USE OF PROGRAM MEMORY .................................................................................. 14 14 14 15 15 16 3. ADDRESS STACK REGISTER (ASR) ....................................................................................... 3.1 3.2 3.3 OUTLINE AND CONFIGURATION OF ADDRESS STACK REGISTER ..................................... ADDRESS STACK REGISTER OPERATION ............................................................................... NOTES ON USE OF ADDRESS STACK REGISTER ................................................................... 17 17 17 17 4. DATA MEMORY (RAM) .............................................................................................................. 4.1 4.2 4.3 4.4 OUTLINE OF DATA MEMORY ...................................................................................................... CONFIGURATION AND FUNCTIONS OF DATA MEMORY ........................................................ DATA MEMORY ADDRESSING .................................................................................................... NOTES ON USING DATA MEMORY ............................................................................................. 18 18 18 21 21 5. SYSTEM REGISTER (SYSREG) ................................................................................................ 5.1 5.2 5.3 OUTLINE OF SYSTEM REGISTER ............................................................................................... PROGRAM STATUS WORD (PSWORD) ...................................................................................... NOTES ON USING SYSTEM REGISTER ..................................................................................... 22 22 23 24 6. GENERAL-PURPOSE REGISTER (GR) ................................................................................... 6.1 6.2 6.3 OUTLINE OF GENERAL-PURPOSE REGISTER ......................................................................... GENERAL-PURPOSE REGISTER ADDRESS GENERATION WITH INSTRUCTIONS ............. NOTES ON USING GENERAL-PURPOSE REGISTER ............................................................... 25 25 25 26 7. ARITHMETIC LOGIC UNIT (ALU) BLOCK ............................................................................... 7.1 7.2 7.3 7.4 OVERVIEW ...................................................................................................................................... CONFIGURATION AND FUNCTIONS OF THE COMPONENTS OF THE ALU BLOCK ........... ALU OPERATIONS ......................................................................................................................... NOTES ON USING THE ALU ........................................................................................................ 27 27 28 28 31 5 PD17015 8. DATA BUFFER (DBF) ................................................................................................................ 8.1 8.2 8.3 OVERVIEW ...................................................................................................................................... RELATIONSHIP BETWEEN THE PERIPHERAL HARDWARE AND DATA BUFFER .............. NOTES ON USING THE DATA BUFFER ...................................................................................... 32 32 34 34 9. GENERAL-PURPOSE PORTS ................................................................................................... 9.1 9.2 9.3 9.4 OVERVIEW ...................................................................................................................................... GENERAL-PURPOSE I/O PORTS (P0A0 AND POA1 PINS) ....................................................... GENERAL-PURPOSE INPUT PORT (P0B0 TO P0B2 PINS) ....................................................... GENERAL-PURPOSE OUTPUT PORTS (P0A2, P0A3, P0C0 TO P0C3, AND P0D0 PINS) ....... 35 35 36 38 39 10. TIMERS ....................................................................................................................................... 10.1 10.2 OVERVIEW ...................................................................................................................................... BASIC TIMERS 0 AND 1 ................................................................................................................ 41 41 41 11. PLL FREQUENCY SYNTHESIZER ............................................................................................ 11.1 11.2 11.3 11.4 11.5 11.6 11.7 GENERAL ........................................................................................................................................ INPUT SWITCHING BLOCK AND PROGRAMMABLE DIVIDER ................................................ REFERENCE FREQUENCY GENERATOR .................................................................................. PHASE COMPARATOR (-DET), CHARGE PUMP AND UNLOCK DETECTION BLOCK ....... PLL DISABLED STATE .................................................................................................................. PLL FREQUENCY SYNTHESIZER USE ....................................................................................... STATE AT RESET .......................................................................................................................... 50 50 51 56 57 61 61 64 12. BEEP ........................................................................................................................................... 12.1 12.2 CONFIGURATION AND FUNCTIONS ........................................................................................... STATE AT RESET .......................................................................................................................... 65 65 66 13. LCD CONTROLLER/DRIVER .................................................................................................... 13.1 13.2 13.3 13.4 13.5 13.6 13.7 OVERVIEW ...................................................................................................................................... LCD DRIVING VOLTAGE GENERATION BLOCK ....................................................................... LCD SEGMENT REGISTER ........................................................................................................... TIMING CONTROL BLOCKS FOR OUTPUTTING COMMON SIGNAL AND SEGMENT SIGNAL ......................................................................................................................... COMMON SIGNAL AND SEGMENT SIGNAL OUTPUT WAVEFORMS ..................................... USING THE LCD CONTROLLER/DRIVER ................................................................................... STATE AT RESET .......................................................................................................................... 67 67 68 69 71 72 74 76 14. STANDBY .................................................................................................................................... 14.1 14.2 14.3 14.4 14.5 14.6 STANDBY FUNCTIONS ................................................................................................................. HALT FUNCTION ............................................................................................................................ CLOCK-STOP FUNCTION ............................................................................................................. DEVICE OPERATION IN THE HALT AND CLOCK-STOP STATES ........................................... PIN PROCESSING CAUTIONS IN HALT STATE AND CLOCK-STOP STATE ......................... DEVICE OPERATION CONTROL BY THE CE PIN ..................................................................... 77 77 79 83 86 87 89 6 PD17015 15. RESET ......................................................................................................................................... 15.1 15.2 15.3 15.4 15.5 OUTLINE OF RESET FUNCTION .................................................................................................. POWER-ON RESET ........................................................................................................................ CE RESET ....................................................................................................................................... RELATIONSHIP BETWEEN CE RESET AND POWER-ON RESET ........................................... POWER FAILURE DETECTION .................................................................................................... 91 91 92 95 99 101 16. INSTRUCTION SET .................................................................................................................... 106 16.1 16.2 16.3 LIST OF INSTRUCTION SET ......................................................................................................... INSTRUCTIONS .............................................................................................................................. ASSEMBLER (AS17K) BUILT-IN MACRO INSTRUCTIONS ....................................................... 106 107 109 17. RESERVED SYMBOLS .............................................................................................................. 110 17.1 17.2 17.3 17.4 17.5 17.6 17.7 SYSTEM REGISTER (SYSREG) .................................................................................................... DATA BUFFER (DBF) .................................................................................................................... LCD SEGMENT REGISTER ........................................................................................................... PERIPHERAL CONTROL REGISTER ........................................................................................... PERIPHERAL HARDWARE REGISTER ....................................................................................... 110 110 111 112 112 PORT REGISTER ............................................................................................................................ 111 OTHERS .......................................................................................................................................... 112 18. ELECTRICAL CHARACTERISTICS .......................................................................................... 113 19. PACKAGE DRAWING ................................................................................................................ 115 20. RECOMMENDED SOLDERING CONDITIONS ......................................................................... 116 APPENDIX DEVELOPMENT TOOLS............................................................................................. 117 7 PD17015 1. PIN FUNCTIONS 1.1 PIN FUNCTIONS Pin No. 37 38 1 2 | 5 6 Symbol P0B0 | P0B2 P0C0 | P0C3 P0D0/ BEEP 3-bit input port. Function Output type Input with a pulldown resistor At power-on reset Input 4-bit CMOS output port CMOS push-pull Low-level output 1-bit general-purpose output port and BEEP signal output CMOS push-pull Low-level output * P0D0 * 1-bit output port * BEEP * 3-kHz BEEP output 7 | 10 P0A0 | P0A3 2-bit I/O and output ports CMOS push-pull Input (P0A0, P0A1) * P0A0, P0A1 * 2-bit I/O port * Input or output mode can be specified in units of bits. * P0A2, P0A3 * 2-bit output port 11 CE XOUT XIN VDD Input pin for the PD17015 operation selection and reset signal -- Low-level output (P0A2, P0A3) Input -- 5 12 13 14 Pins for connecting the crystal (75 kHz) for system clock oscillation. CMOS push-pull (XOUT) Load capacity: CI = 12 pF, CO = 33 pF Main power supply pin The pin supplies a voltage of 1.8 to 3.6 V (TA = -10 to +50 C) to enable all functions. Note that the voltage applied to each of the other pins must not exceed the voltage applied to the VDD pin. Ground pin Output from the charge pump of the PLL frequency synthesizer. -- -- 15 16 GND EO -- CMOS tristate output -- -- Floating 17 VREG Output pin for the PLL voltage regulator. Connect this pin to GND through a 0.1-F capacitor. -- VREG (17) 0.1 F 18 19 VCOH VCOL Local PLL oscillator frequency input -- Floating 8 PD17015 1.2 EQUIVALENT CIRCUIT OF EACH PIN (1) P0A (P0A0, P0A1): (I/O) VDD VDD (2) P0B (P0B0, P0B1, P0B2): (Input) VDD High on-state resistance (3) P0A (P0A2, P0A3) P0C (P0C0, POC1, POC2, POC3) P0D (P0D0, BEEP) LCD0 - LCD8 EO VDD (Output) 9 PD17015 (4) COM0 - COM3: (Output) VLCD0 VLCD1 (5) VCOL: (Input) High on-state resistance VDD High on-state resistance VDD 10 PD17015 (6) VCOH: (Input) High on-state resistance VDD VDD (7) CE: (Schmitt-triggered input) VDD (8) XOUT: (Output), XIN: (Input) High on-state resistance VDD VDD XIN XOUT 11 PD17015 5 1.3 HANDLING UNUSED PINS When connecting unused pins, the following conditions and handling are recommended: Table 1-1 Handling Unused Pins Pin Port pin P0B0-P0B2 P0C0-P0C3 P0D0/BEEP P0A2, P0A3 P0A0, P0A1 I/ONote 2 Input I/O type Recommended handling when unused Connect each pin to ground through a resistorNote 1. Leave open. CMOS push-pull output Set these pins to input mode by software. Then, connect each pin to VDD or ground through a resistorNote 1. -- Leave open. Connect to VDD through a resistorNote 1. Leave open. Leave open. Leave open. Set these pins to the disabled state by software. Then, leave these pins open. -- -- Leave open. Leave open. Non-port pin CAP0, CAP1 CE COM0-COM3 EO LCD0-LCD8 VCOH, VCOL Input Output Output Output Input VLCD0, VLCD1 VREG Notes 1. When a pin is pulled up (connected to VDD through a resistor) or pulled down (connected to ground through a resistor) outside the chip, caution is required. When using high-resistance pull-up or pull-down resistors, the pin approaches high-impedance and the consumption (through) current increases. Although the optimum pull-up or pull-down resistor varies with the application circuit, in general the use of a resistor of 10 to 100 kilohms is recommended. 2. I/O port is applicable at power-on, at clock stop, at CE reset, or in input mode. 12 PD17015 1.4 NOTES ON USE OF THE CE PIN The CE pin has the test mode selecting function for testing the internal operation of the PD17015 (IC test), besides the functions shown in Section 1.1. Applying a voltage exceeding VDD to the CE pin causes the PD17015 to enter the test mode. When noise exceeding VDD comes in during normal operation, the device is switched to the test mode. For example, if the wiring from the CE pin is too long, noise may be induced on the wiring, causing this mode switching. When installing the wiring, lay the wiring in such a way that noise is suppressed as much as possible. If noise yet arises, use an external part to suppress it as shown below. * Connect a diode with low VF between the pin and VDD. VDD VDD VDD VDD * Connect a capacitor between the pin and VDD. Diode with low VF CE CE 13 PD17015 2. PROGRAM MEMORY (ROM) 2.1 OUTLINE OF PROGRAM MEMORY Fig. 2-1 outlines program memory. As shown in Fig. 2-1, program memory is addressed with a program counter. Program memory is used to store programs. The program counter is used to specify an address in program memory. Fig. 2-1 Outline of Program Memory Program counter Addressing Program memory Instruction 2.2 PROGRAM MEMORY CONFIGURATION Fig. 2-2 shows the configuration of program memory. As shown in Fig. 2-2, program memory consists of 1528 steps x 16 bits. Program memory therefore has addresses 0000H to 05F7H. All PD17015 instructions are 16-bit one-word instructions. Each instruction can be stored at a single address of program memory. Fig. 2-2 Program Memory Configuration 0000H 16 bits 1.5K steps 05F7H Undefined 07FFH 14 PD17015 2.3 PROGRAM COUNTER Fig. 2-3 shows the configuration of the program counter. As shown in Fig. 2-3, the program counter consists of a 11-bit binary counter. The program counter is used to specify an address in program memory. Fig. 2-3 Program Counter Configuration MSB PC10 PC9 PC8 PC7 PC6 PC5 11 bits PC4 PC3 PC2 PC1 LSB PC0 2.4 PROGRAM FLOW The execution flow of a program is controlled with the program counter, which specifies an address in program memory. This section describes the operation of several types of instructions. Fig. 2-4 shows the value set in the program counter when each instruction is executed. 2.4.1 Direct branch ("BR addr") A direct branch instruction can branch to all addresses of program memory, 0000H to 05F7H. 2.4.2 Subroutines To call a subroutine, a direct subroutine call ("CALL addr") is used. A direct subroutine call instruction can call a subroutine starting at any address in program memory, 0000H to 05F7H. RET or RETSK instruction is used as the return instruction from a subroutine. Fig. 2-4 Program Counter Value When Each Instruction Is Executed Program counter Instruction BR CALL RET RETSK At power-on reset or CE reset 0 addr addr b10 b9 Value of program counter b8 b7 b6 b5 b4 b3 b2 b1 b0 Instruction operand (addr) Contents of address stack register (return address) 0 0 0 0 0 0 0 0 0 0 15 PD17015 2.5 NOTES ON USE OF PROGRAM MEMORY Although only addresses 0000H to 07FFH can be specified by the program counter, the valid program memory addresses are 0000H to 05F7H. Program memory addresses 05F8H to 07FFH contain undefined values. Therefore, note the following: (1) Do not write instructions to addresses 05F8H to 07FFH. (2) Use a branch instruction to write instructions at address 05F7H. (3) Do not branch to addresses 05F8H to 07FFH. 16 PD17015 3. ADDRESS STACK REGISTER (ASR) 3.1 OUTLINE AND CONFIGURATION OF ADDRESS STACK REGISTER The address stack register is used to store the return address when a subroutine call instruction is executed. Fig. 3-1 shows the configuration of the address stack registers. As shown in Fig. 3-1, there is one address stack register, consisting of 11 bits. Fig. 3-1 Configuration of Address Stack Registers Address stack register (ASR) Bit b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 The return address of the program is stored when a subroutine call instruction is executed. 3.2 ADDRESS STACK REGISTER OPERATION When a subroutine call instruction is executed, the return address is stored in the address stack register. When a return instruction is executed, the contents (return address) of the address stack register are read back into the program counter (see Table 3-1). At power-on reset, the contents of the address stack register are undefined. At CE reset, or when the clock stop instruction is executed, the contents of the address stack register are retained. Table 3-1 Program Counter Operation Upon Execution of a Subroutine Call Instruction Instruction CALL addr 1 Operation Stores the program counter value to the address stack register. Transfers the value specified with an operand (addr) to the program counter. 2 RET RETSK Reads the value of the address stack register back into the program counter. 3.3 NOTES ON USE OF ADDRESS STACK REGISTER Note that a subroutine call of more than one level cannot be used because the address stack register has a oneregister configuration consisting of 11 bits. 17 PD17015 4. DATA MEMORY (RAM) 4.1 OUTLINE OF DATA MEMORY Fig. 4-1 outlines the data memory. As shown in Fig. 4-1, the data memory consists of a general-purpose data memory, system registers, data buffer, general-purpose registers, LCD segment registers, port registers, and peripheral control registers. The data memory is used to store data, transfer data to and from peripheral hardware, set peripheral hardware condition, set display data, transfer data to and from ports, and control the CPU. Fig. 4-1 Outline of Data Memory Peripheral hardware 0 0 Used as the general-purpose register 1 Low address Data transfer 1 2 3 4 5 Column address 6 7 8 9 A B C D E F Data buffer (DBF) 2 3 4 5 6 7 Port register System register LCD segment register Peripheral control register Data memory Data transfer Data transfer Port Setting condition LCD Peripheral hardware 4.2 CONFIGURATION AND FUNCTIONS OF DATA MEMORY Fig. 4-2 shows the configuration of the data memory. As shown in Fig. 4-2, the data memory consists of 128 nibbles made up of row addresses 0H to 7H by column addresses 0H to FH. The data memory is divided into the functional blocks described in Sections 4.2.1 through 4.2.7. By using data memory manipulation instructions, 4-bit operations, comparison, decision, and transfer operation can be performed for the data memory. Table 4-1 indicates the data memory manipulation instructions. 4.2.1 System Register (SYSREG) A system register, allocated to addresses 74H to 7FH, directly controls the CPU. With the PD17015, only PSWORD (program status word: addresses 7EH and 7FH) can be manipulated. See Chapter 5 for details. 18 PD17015 4.2.2 Data Buffer (DBF) A data buffer, allocated at addresses 0CH-0FH, transfers data to and from peripheral hardware. With the PD17015, the data buffer transfers data to and from the PLL data register (peripheral address 41H) when the data (16 bits) of the PLL frequency division ratio is set or read. See Chapter 8 for details. 4.2.3 General-Purpose Register (GR) With the PD17015, the general-purpose register cannot be moved because it is fixed to low address 0 of data memory (i.e., addresses 00H to 0FH). The general-purpose register can be used to perform an operation on data, or transfer data to and from the data memory, by means of a single instruction. The general-purpose register, like other data memory, can be controlled by issuing data memory manipulation instructions. For details, see Chapter 6. 4.2.4 LCD Segment Data Register (LCD Segment Register) The LCD segment register, allocated at addresses 61H to 69H, sets the display data for the LCD controller/driver. For details, see Chapter 13. 4.2.5 Port Data Register (Port Register) The port register, allocated at addresses 70H to 73H, sets the output data for each general-purpose port and reads the input port data. For details, see Chapter 9. 4.2.6 Peripheral Control Register The peripheral control register, allocated at addresses 6AH to 6FH, sets the condition of the peripheral hardware (such as PLL or timer). 4.2.7 General-Purpose Data Memory The general-purpose data memory consists of data memory other than the system register, LCD segment register, port register, and peripheral control register. For the PD17015, 97 nibbles (97 x 4 bits: addresses 00H to 60H) can be used as general-purpose data memory. 19 20 0 0 1 2 3 4 5 1 2 3 4 5 6 LCDD8 LCDD7 LCDD6 LCDD5 P0A P 0 7A 3 P 0 A 2 P 0 A 1 P 0 A 00 P0B P 0 B 2 P 0 B 1 P 0 B 0 P 0 C 3 P0C P 0 C 2 P 0 C 1 P0D P 0 C 0000 P 0 D 0 AR0 Fig. 4-2 Configuration of Data Memory 6 7 8 9 A B C DBF3 D DBF2 E DBF1 F DBF0 LCDD4 LCDD3 LCDD2 LCDD1 LCDD0 L C D E N LCDE BPP E00 EAA PBB 0II S OO E10 L PLLMD CEJDG PLLULJDG BTM0CYJDG BTM1CYJDG PPPP C P B B E L T T LLLL L M M LLLL 0 1 MMR R 0 0 0 0 0 0U0 0 0 C0 0 0C L DDF F Y Y 1 0CC KK 10 System register AR1 AR2 AR3 WR BANK IXH MPH IXM MPH IXL RPH RPL PSW B CC Z CMY DP 0 0 PD17015 PD17015 Table 4-1 List of Data Memory Manipulation Instructions Function Operation Addition Instruction ADD ADDC Subtraction SUB SUBC AND OR XOR Comparison SKE SKGE SKLT SKNE MOV LD ST Decision SKT SKF Logical Transfer 4.3 DATA MEMORY ADDRESSING Fig. 4-3 shows how a data memory address is specified. A data memory address is specified with a bank, row address, and column address. A row address and column address are directly specified with a data memory manipulation instruction. Fig. 4-3 Data Memory Addressing Row address b2 Data memory address M b1 b0 Column address b3 b2 b1 b0 Instruction operand 4.4 NOTES ON USING DATA MEMORY Upon power-on reset, the contents of the general-purpose data memory are undefined. Initialize the general-purpose data memory as required. 21 PD17015 5. SYSTEM REGISTER (SYSREG) 5.1 OUTLINE OF SYSTEM REGISTER Fig. 5-1 shows where the system registers are located in the data memory, and also outlines the system register. As shown in Fig. 5-1, a system register is allocated to data memory addresses 74H-7FH. The system registers are allocated in the data memory, so that the system registers can be manipulated using any manipulation instructions. For the PD17015, only the program status word (PSWORD: 7EH and 7FH) in the system register (addresses 74H to 7FH) can be manipulated. Fig. 5-1 Location on Data Memory and Outline of System Registers Column address 0 0 1 1 2 3 4 5 6 7 8 9 A B C D E F Data memory Low address 2 3 4 5 6 7 System register Address 74H 75H 7DH 7EH 7FH Program status word (PSWORD) Operation control Name Fixed to 0 Outline 22 PD17015 5.2 5.2.1 PROGRAM STATUS WORD (PSWORD) Format of Program Status Word Fig. 5-2 shows the format of the program status word. As shown in Fig. 5-2, the program status word consists of 5 bits: the least significant bit of 7EH (RPL) of the system register, and the 4 bits of address 7FH (PSW) of the system register. Bit 0 of 7FH is always 0. A different function is assigned to each bit of the program status word; the program status word consists of a BCD flag (BCD), compare flag (CMP), carry flag (CY), zero flag (Z), and index enable flag (IXE). Fig. 5-2 Format of Program Status Word Address Register Symbol Bit b3 7EH 7FH Program status word (PSWORD) RPL b2 b1 b0 B C D b3 C M P PSW b2 C Y b1 Z 0 0 0 0 b0 Data Power-on Clock stop CE 0 0 0 0 0 0 5.2.2 Program Status Word Functions The program status word is used to set conditions for transfer instructions and operations by the arithmetic logic unit (ALU), and also to indicate the states of the results of operations. Fig. 5-3 outlines the function of each flag of the program status word. See Chapter 7 for details. Upon reset 23 PD17015 Fig. 5-3 Outline of Function of Each Flag of Program Status Word Program status word (PSWORD) RPL b3 b2 b1 b0 B C D b3 C M P PSW b2 C Y b1 Z 0 b0 0 0 0 Flag name Zero flag (Z) Function Used to indicate that the result of an arithmetic operation is 0. Note that the states of 0 and 1 differ, depending on the value of the compare flag. Used to indicate the ocurrence of a carry or borrow as the result of an addition or subtraction instruction executed. This flag is cleared to 0 when neither a carry nor a borrow is produced. This flag is set to 1 when a carry or borrow is produced. This flag is used also as a shift bit for the RORC r instruction. Used to specify whether to store the result of an arithmetic operation in a general-purpose register or data memory area. 0 : Stores the result. 1 : Does not store the result. Used to specify whether to perform an arithmetic operation in decimal. 0 : Performs a binary operation. 1 : Performs a decimal operation. Carry flag (CY) Compare flag (CMP) BCD flag (BCD) 5.2.3 Notes on Using Program Status Word When an arithmetic instruction (addition or subtraction) is executed for the program status word, the result of the arithmetic operation is stored. If an operation is performed which produces the result 0000B with a carry, for example, 0000B is stored in the PSW. 5.3 NOTES ON USING SYSTEM REGISTER Those data items in the program status word that are always set to 0 are not affected by an attempt to execute a write instruction. When those data items in the program status word that are always set to 0 are read, 0 is read. 24 PD17015 6. GENERAL-PURPOSE REGISTER (GR) 6.1 OUTLINE OF GENERAL-PURPOSE REGISTER Fig. 6-1 outlines the general-purpose register. For the PD17015, the general-purpose register is fixed to low address 0 of the data memory, consisting of 16 nibbles (00H to 0FH, 16 x 4 bits). 16 nibbles of the row address 0 specified as a general-purpose register is used to perform an operation with or transfer data to and from the data memory. This means that an operation or data transfer between data memory areas can be performed with one instruction. As with other data memory areas, a general-purpose register can be controlled using data memory manipulation instructions. Fig. 6-1 Outline of General-Purpose Register Column address 0 0 1 Low address 1 2 3 4 5 6 7 8 9 A B C D E F General-purpose register Transfer, operation 2 3 4 5 6 7 System register Data memory 6.2 GENERAL-PURPOSE REGISTER ADDRESS GENERATION WITH INSTRUCTIONS Sections 6.2.1 and 6.2.2 below describe general-purpose register address generation when each instruction is executed. For the detailed operation of each instruction, see Chapter 7. 6.2.1 Addition Instructions (ADD r,m, ADDC r,m) Subtraction Instructions (SUB r,m, SUBC r,m) Logical Operation Instructions (AND r,m, OR r,m, XOR r,m) Direct Transfer Instructions (LD r,m, ST m,r), and Rotate Instruction (RORC r) Fig. 6-2 indicates a general-purpose register address R specified by operand r of an instruction. Operand r specifies only a column address. 25 PD17015 Fig. 6-2 General-Purpose Register Address Generation Low address b2 General-purpose register address R b1 b0 b3 Column address b2 r b1 b0 Fixed to 0 6.2.2 Indirect Transfer Instructions (MOV @r,m, MOV m,@r) Fig. 6-3 indicates a general-purpose register address R specified by operand r of an instruction, and an indirect transfer address specified by @R. Fig. 6-3 General-Purpose Register Address Generation Low address b2 General-purpose register address R b1 b0 b3 Column address b2 r b1 b0 Fixed to 0 Indirect transfer address @R Fixed to 0 Contents of R 6.3 NOTES ON USING GENERAL-PURPOSE REGISTER No instruction is available for operation between a general-purpose register and immediate data. To execute an operation instruction between a general-purpose register and immediate data, the general-purpose register area must be handled as a data memory area. 26 PD17015 7. ARITHMETIC LOGIC UNIT (ALU) BLOCK 7.1 OVERVIEW Fig. 7-1 is an overview of the ALU block. As shown in Fig. 7-1, the ALU block consists of the ALU, temporary storage registers A and B, program status word, decimal conversion circuit, and data memory address controller. The ALU performs arithmetic and logic operations on the 4-bit data in the data memory and performs discrimination, comparison, rotation, and transfer. Fig. 7-1 Overview of the ALU Block Data bus Address controller Temporary storage register A Temporary storage register B Program status word Detecting a carry, borrow, or zero Setting decimal calculation or result storage ALU * Arithmetic operation * Logic operation * Bit discrimination * Comparative discrimination * Rotation * Transfer Data memory Decimal conversion 27 PD17015 7.2 7.2.1 CONFIGURATION AND FUNCTIONS OF THE COMPONENTS OF THE ALU BLOCK ALU In response to a programmed instruction, the ALU performs 4-bit arithmetic or logic processing, bit discrimination, comparative discrimination, rotation, or transfer. 7.2.2 Temporary Storage Registers A and B Temporary storage registers A and B temporarily hold the 4-bit data. These registers are automatically used when an instruction is executed. They cannot be controlled by a program. 7.2.3 Program Status Word A program status word controls the operation of the ALU and holds the status of the ALU. For details of the program status word, see Section 5.2. 7.2.4 Decimal Conversion Circuit If the BCD flag of the program status word is set to 1 when an arithmetic operation is executed, the decimal conversion circuit converts the results of the arithmetic operation to a decimal number. 7.2.5 Address Controller The address controller specifies an address in data memory. 7.3 ALU OPERATIONS Table 7-1 lists the operations performed by the ALU when instructions are executed. Table 7-2 lists the converted decimal data used in decimal operations. 28 PD17015 Table 7-1 ALU Operations ALU function Operation difference due to program status word (PSWORD) Instruction Value Value of the of the BCD flag CMP flag 0 0 Operation Binary operation The result is stored. Binary operation The result is not stored. Decimal operation The result is stored. Decimal operation The result is not stored. Set by a carry or borrow. Otherwise, the flag is reset. Operation of the CY flag Operation of the Z flag Set if the operation result is 0000B. Otherwise, the flag is reset. Retains the status if the operation result is 0000B. Otherwise, the flag is reset. Set if the operation result is 0000B. Otherwise, the flag is reset. Retains the status if the operation result is 0000B. Otherwise, the flag is reset. r, m Addition ADD m, #n4 r, m ADDC m, #n4 r, m SUB m, #n4 r, m SUBC m, #n4 r, m OR 0 1 Subtraction 1 0 1 1 Logic operation m, #n4 r, m Optional Optional (hold) (hold) Not changed Retains the previous state. Retains the previous state. AND m, #n4 r, m XOR m, #n4 Discrimination SKT SKF SKE SKNE SKGE SKLT LD m, #n m, #n m, #n4 Optional Optional (reset) (hold) Not changed Retains the previous state. Retains the previous state. Comparison m, #n4 Optional Optional (hold) (hold) m, #n4 m, #n4 r, m m, r m, #n4 Optional Optional (hold) (hold) Not changed Retains the previous state. Retains the previous state. Transfer ST Not changed Retains the previous state. Retains the previous state. MOV @r, m m, @r Value of b0 of the generalpurpose register Rotation RORC r Optional Optional (hold) (hold) Not changed Retains the previous state. 29 PD17015 Table 7-2 Converted Decimal Data Operation result Hexadecimal addition CY Operation result 0000B 0001B 0010B 0011B 0100B 0101B 0110B 0111B 1000B 1001B 1010B 1011B 1100B 1101B 1110B 1111B 0000B 0001B 0010B 0011B 0100B 0101B 0110B 0111B 1000B 1001B 1010B 1011B 1100B 1101B 1110B 1111B Decimal addition CY 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Operation result 0000B 0001B 0010B 0011B 0100B 0101B 0110B 0111B 1000B 1001B 0000B 0001B 0010B 0011B 0100B 0101B 0110B 0111B 1000B 1001B 1110B 1111B 1100B 1101B 1110B 1111B 1100B 1101B 1010B 1011B 1100B 1101B Operation result Hexadecimal addition CY Operation result 0000B 0001B 0010B 0011B 0100B 0101B 0110B 0111B 1000B 1001B 1010B 1011B 1100B 1101B 1110B 1111B 0000B 0001B 0010B 0011B 0100B 0101B 0110B 0111B 1000B 1001B 1010B 1011B 1100B 1101B 1110B 1111B Decimal addition CY 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Operation result 0000B 0001B 0010B 0011B 0100B 0101B 0110B 0111B 1000B 1001B 1100B 1101B 1110B 1111B 1100B 1101B 1110B 1111B 1100B 1101B 1110B 1111B 0000B 0001B 0010B 0011B 0100B 0101B 0110B 0111B 1000B 1001B 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 -16 -15 -14 -13 -12 -11 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Remark Correct decimal conversion is not possible in the shaded area. 30 PD17015 7.4 7.4.1 NOTES ON USING THE ALU Notes on Using the Program Status Word for Operations After an arithmetic operation has been performed on the program status word, the operation result is held in the program status word. The CY and Z flags of the program status word are usually set or reset according to the result of the arithmetic operation. If the arithmetic operation is performed on the program status word itself, the result of the operation is stored and a carry, borrow, or zero cannot be discriminated. If the CMP flag is set, the result of the arithmetic operation is not stored and the CY and Z flags are set to 1 or cleared to 0 as usual. 7.4.2 Notes on Performing Decimal Operations A decimal operation can be carried out only when the operation result is within the following ranges: (1) The result of addition is between 0 and 19 in decimal. (2) The result of subtraction is between 0 and 9 or -10 and -1 in decimal. If a decimal operation exceeding the above ranges is performed, the CY flag is set, resulting in a value greater than or equal to 1010B (0AH). 31 PD17015 8. DATA BUFFER (DBF) 8.1 OVERVIEW Fig. 8-1 shows an overview of the data buffer. The data buffer is configured in data memory and used to transfer data to and from peripheral hardware. Fig. 8-1 Overview of the Data Buffer Data buffer Reading data (GET instruction) Writing data (PUT instruction) Peripheral hardware Fig. 8-2 shows the configuration of the data buffer. As shown in Fig. 8-2, the data buffer consists of 16 bits of addresses 0CH to 0FH in data memory. The most significant bit (MSB) of the 16-bit data is bit b3 at address 0CH. The least significant bit (LSB) is bit b0 at address 0FH. The data buffer is configured in data memory and can thus be manipulated by any data memory manipulation instruction. 32 PD17015 Fig. 8-2 Configuration of the Data Buffer Column address 0 0 1 2 1 2 3 4 5 6 7 8 9 A B C D E F Data buffer (DBF) Low address 3 4 5 6 7 Data memory System register Data memory Address Bit Bit Symbol 0CH 0DH 0EH 0FH b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 DBF3 DBF2 DBF1 DBF0 < M S B < L S B Data buffer Data < < Data 8.1.1 Instructions for Controlling the Peripheral Hardware (PUT, GET) The PUT and GET instructions operate as described below: (1) GET DBF, p Data in the peripheral register at address p is read and written into the data buffer. (2) PUT p, DBF Data in the data buffer is set in the peripheral register at address p. 33 PD17015 8.2 Relationship between the Peripheral Hardware and Data Buffer Table 8-1 indicates the relationship between the peripheral hardware and data buffer. With the PD17015, the DBF transfers data to and from the PLL data register (peripheral address 41H) when data (16 bits) of the PLL frequency division ratio is set or read. Table 8-1 Relationship between the Peripheral Hardware and Data Buffer Peripheral register used to transfer data to or from the data buffer Peripheral hardware Name Symbol Peripheral Instruction that address can be used Number of data buffer input bits PLL frequency synthesizer PLL data register PLLR 41H GET/PUT 16 16 Function Number of bits actually used Description Sets N, by which PLL frequency is divided. 8.3 NOTES ON USING THE DATA BUFFER If an attempt is made to read the data at an unused peripheral address, an undefined value will be read. If writing to the unused address is attempted, nothing changes. 34 PD17015 9. GENERAL-PURPOSE PORTS A general-purpose port outputs high and low signals to external circuits and reads high and low signals from the external circuits. 9.1 OVERVIEW Table 9-1 indicates the relationship between the ports and port registers. General-purpose ports are classified into three types: I/O ports, input ports, and output ports. I/O port is a bit I/O port, whose bit (each pin) can be set to input or output mode. Table 9-1 Relationship between Ports (Pins) and Port Registers Pin Port No. Pin name I/O Address 7 Port 0A 8 9 10 37 38 Port 0B 1 P0B2 No target pin 2 3 Port 0C 4 5 6 Port 0D No target pin P0C2 P0C3 P0D0 Output 73H P0D P0C0 P0C1 Output 72H P0C P0A0 P0A1 P0A2 P0A3 P0B0 P0B1 Input 71H P0B Symbol Data setting method Port register (data memory) Bit symbol (reserved word) b0 b1 70H Output P0A b2 b3 b0 b1 b2 b3 b0 b1 b2 b3 b0 b1 b2 b3 P0A2 P0A3 P0B0 P0B1 P0B2 -- P0C0 P0C1 P0C2 P0C3 P0D0 -- -- -- Fixed to 0. Switching to BEEP output is performed by the BEEP0SEL flag. Fixed to 0. P0A0 P0A1 Remarks I/O (bit I/O) I/O switching is performed by the P0ABIO0 or P0ABIO1 flag. 35 PD17015 9.2 9.2.1 GENERAL-PURPOSE I/O PORTS (P0A0 and P0A1 pins) Configurations of the I/O ports The configurations of the I/O ports are shown below. (1) P0A0 and P0A1 pin I/O switching flag VDD Output latch Write instruction Port register (1 bit) VDD 1 Read instruction 0 9.2.2 Using the I/O Port The P0ABIO0 or P0ABIO1 flag of the LCD enable register sets the I/O port to input or output mode. P0A0 and P0A1 pins are bit I/O ports, each bit of which (each pin) can be set to input or output mode. To set the output data, write the data to the corresponding port register. To read the input data, execute an instruction to read the data. 9.2.3 Control Registers of the I/O Ports The P0ABIO0 and P0ABIO1 flags of the LCD enable register set P0A0 and P0A1 pins in input or output mode, respectively. Fig. 9-1 shows the configuration and functions of the LCD enable register. 36 PD17015 Fig. 9-1 Configuration and Functions of the LCD Enable Registers Flag symbol Register b3 L C D E N b2 B E E P 0 S E L b1 P 0 A B I O 1 b0 P 0 A B I O 0 Address Read/write LCD enable register 6AH R/W Sets pin P0A0 to input or output mode. 0 1 Sets pin P0A0 to input mode. Sets pin P0A0 to output mode. Sets pin P0A1 to input or output mode. 0 1 Sets pin P0A1 to input mode. Sets pin P0A1 to output mode. Upon reset Power-on Clock stop CE 0 0 0 0 Hold 0 0 0 0 9.2.4 Using an I/O Port as an Input Port Select the pin to be set to input mode, using the P0ABIO0 and P0ABIO1 flags of the LCD enable register. The P0A0 and P0A1 pins can be set to input mode bit by bit. The specified input pin enters the floating (Hi-Z) status and waits for the input of an external signal. To read the input data, execute an instruction to read the contents of the port register P0A (such as SKT). If the signal input to the pin is high, 1 is read from the corresponding port register. If the input signal is low, 0 is read from the port register. If a write instruction (such as MOV) is executed for the port register corresponding to an input port, the contents of the output latch are rewritten. 9.2.5 Using an I/O Port as an Output Port Select the pin to be set to output mode, using the P0ABIO0 and P0ABIO1 flags of the LCD enable register. The P0A0 and P0A1 pins can be set in the output mode bit by bit. The specified output pin outputs the contents of the output latch. To set the output data, execute a write instruction (such as MOV) for the port register P0A. To output a high signal to a pin, write 1. To output a low signal, write 0. To set a port to the floating state, set the port to input mode. If a read instruction (such as SKT) is executed for the port register corresponding to an output port, the contents of the output latch are read. 37 PD17015 5 Caution If a read instruction (such as SKT) is executed for a port register specified as an output port, the contents of the output latch and the read data may differ because the status of the output pin is read as is. 9.2.6 Statuses of the I/O Ports upon Reset (1) At power-on reset All pins are set to input mode. 5 The contents of the output latches are reset to 0. (2) At CE reset All pins are set to input mode. The contents of the output latches are retained. (3) At a clock-stop All pins are set to input mode. The contents of the output latches are retained. (4) In the halt state The previous statuses are retained. 9.3 9.3.1 GENERAL-PURPOSE INPUT PORT (P0B0 to P0B2 pins) Configuration of the Input Port The configuration of the input port is shown below: * P0B (P0B0 to P0B2 pins) Write instruction VDD Port register (1 bit) Input latch Read instruction High on-state resistance Read instruction 38 PD17015 9.3.2 Using the Input Port To read the input data, execute an instruction to read the contents of port register P0B (such as SKT). If the signal input to a pin is high, 1 is read from the corresponding port register. If the input signal is low, 0 is read from the port register. If a write instruction (such as MOV) is executed for a port register, nothing changes. 9.3.3 Notes on Using the Input Port P0B is internally pulled down. 9.3.4 Statuses of the Input Port upon Reset (1) At power-on reset All pins are set to input mode. (2) At CE reset All pins are set to input mode. (3) At a clock-stop All pins are set to input mode. (4) In the halt state The previous statuses are retained. 9.4 9.4.1 GENERAL-PURPOSE OUTPUT PORTS (P0A2, P0A3, P0C0 to P0C3, and P0D0 pins) Configurations of the Output Ports The configurations of the output ports are shown below. * P0A (P0A2 and P0A3 pins), P0C (P0C0 to P0C3 pins), P0D (P0D0 pin) VDD Output latch Write instruction VDD Port register (1 bit) Read instruction 39 PD17015 9.4.2 Using the Output Port The output port outputs the contents of the output latch from each pin. To set the output data, execute a write instruction (such as MOV) for the port register corresponding to each pin. To output a high signal to a pin, write 1. To output a low signal, write 0. 5 Caution If a read instruction (such as SKT) is executed for a port register, the contents of the output latch and the read data may differ because the status of the output pin is read as is. 9.4.3 Statuses of the Output Port upon Reset (1) At power-on reset The contents of the output latches are output. 5 The contents of the output latches are reset to 0. (2) Upon CE reset The contents of the output latch are output. The output latch retains the data existing immediately before the reset. If a pin is directly set to output mode, the previous contents are output. (3) Upon a clock stop All pins are set to input mode. The output latch retains the last data existing immediately before the reset. If a pin is directly set to output mode, the previous contents are output. (4) In the halt state The previous statuses are retained. 40 PD17015 10. TIMERS The timers in the PD17015 are used to manage the time required to execute programs. 10.1 OVERVIEW Fig. 10-1 shows the block diagrams of the timers. The PD17015 contains the following two different timers. * Basic timer 0 * Basic timer 1 Basic timers 0 and 1 are realized by detecting the state of a flip-flops that is set at constant intervals, using software. Fig. 10-1 Overview of Timers 125 ms(8 Hz) Basic timer 0 carry flip-flop Set/clear BTM0CY flag 75 kHz Frequency divider 5 ms(200 Hz) Basic timer 1 carry flip-flop Set/clear BTM1CY flag 10.2 10.2.1 BASIC TIMERS 0 AND 1 Overview of Basic Timers 0 and 1 Basic timer 0 is realized by detecting the state of a basic timer 0 carry flip-flop, using the BTM0CY flag (bit 0 at address 6EH). Basic timer 1 is realized by detecting the state of a basic timer 1 carry flip-flop, using the BTM1CY flag (bit 0 at address 6FH). The contents of the flip-flops correspond to the states of the BTM0CY and BTM1CY flags on a one-to-one basis, respectively. Time intervals (pulses) at which the BTM0CY and BTM1CY flags are set are as follows: BTM0CY flag set pulse: 125 ms (8 Hz) BTM1CY flag set pulse: 5 ms (200 Hz) When the BTM0CY and BTM1CY flags are read-accessed for the first time after a power-on reset, these flags are read as 0. Subsequently, the BTM0CY flag is set to 1 after an interval of 125 ms and the BTM1CY flag is set to 1 after an intervals of 5 ms. Basic timer 0 also controls the timing of the reset (CE reset) by the CE pin. After the CE pin goes from a low level to a high level, a CE reset occurs simultaneously when the BTM0CY flag is set next time. A power failure can therefore be detected by reading the BTM0CY flag when a system reset (power-on or CE reset) occurs. See Chapter 15 for power failure detection. 41 PD17015 10.2.2 Basic Timer 0 Carry Flip-Flop, Basic Timer 1 Carry Flip-Flop, BTM0CY Flag, and BTM1CY Flag The flip-flop is set at constant intervals, and its state is detected using the BTM0CY and BTM1CY flags. The BTM0CY and BTM1CY flags are read-only. These flags are reset by reading their contents using the instructions listed in Table 10-1 (Read & Reset). The BTM0CY and BTM1CY flags are "0" at a power-on reset. It becomes "1" at a CE reset. So, it can be used as a power failure detection flag. Even when power is supplied, the BTM0CY and BTM1CY flags will not be set until their contents have been read using the instructions listed in Table 10-1. Once a read instruction is executed, the flag is set at constant intervals. Fig. 10-2 shows the configuration and function of the basic timer 0 carry flip-flop judge register. Fig. 10-3 shows the configuration and function of the basic timer 1 carry flip-flop judge register. Table 10-1 Instructions Used to Reset the BTM0CY and BTM1CY Flags Mnemonic ADD ADDC SUB SUBC AND OR XOR SKE SKEG SKLT SKNE Operand Mnemonic ADD ADDC SUB SUBC AND OR XOR LD SKT SKF MOV Operand r, m m, #n4 m, #n @r, m m, @rNote Note When the low address of m is 6H, and 0EH or 0FH is written into r. Remark m = 6EH or 6FH 42 PD17015 Fig. 10-2 Configuration of the Basic Timer 0 Carry Flip-Flop Judge Register Flag symbol Register b3 b2 b1 b0 B T M 0 C Y Address Read/write Basic timer 0 carry flip-flop judge register 0 0 0 6EH Read & Reset Detects the state of the basic timer 0 carry flip-flop. 0 1 The basic timer 0 carry flip-flop is not set. The basic timer 0 carry flip-flop is set. Fixed to 0 Upon reset Power-on Clock stop CE 0 0 0 0 1 1 Fig. 10-3 Configuration of the Basic Timer 1 Carry Flip-Flop Judge Register Flag symbol Register b3 b2 b1 b0 B T M 1 C Y Address Read/write Basic timer 1 carry flip-flop judge register 0 0 0 6FH Read & Reset Detects the state of the basic timer 1 carry flip-flop. 0 1 The basic timer 1 carry flip-flop is not set. The basic timer 1 carry flip-flop is set. Fixed to 0 Upon reset Power-on Clock stop CE 0 0 0 0 1 1 43 PD17015 10.2.3 Example of Using Basic Timer 0 A sample program follows. The following program performs process A at every one second. Example M1 LOOP: SKT1 BR ADD SKT1 BR BTM0CY NEXT M1, #0100B CY NEXT ; Adds 4 to M1. ; Branches to NEXT if CY flag is 0. ; Performs process A if CY flag is 1. ; Branches to NEXT if BTM0CY is 0. MEM 0.10H ; 1 second counter Process A NEXT: Process B BR 10.2.4 LOOP ; Performs B and branches to LOOP. Time Interval Error in Basic Timers 0 and 1 The time interval at which the BTM0CY and BTM1CY flags are detected must be shorter than the time interval at which the BTM0CY and BTM1CY flags are set. (See Section 10.2.5.) Assuming that the BTM0CY or BTM1CY flag is detected at intervals of tCHECK and set at intervals of tSET (125 or 5 ms, respectively), the relationship between tCHECK and tSET must be as follows: tCHECK < tSET Under this condition, the time interval error encountered when the BTM0CY and BTM1CY flags are detected is as follows: 0 < error < tSET Fig. 10-4 Basic Timers 0 and 1 Error Related to the Detection Time of the BTM0CY and BTM1CY Flags BTM0CY flag set pulse H BTM1CY flag set pulse L tSET BTM0CY flag 1 BTM1CY flag 0 tCHECK1 SKT1 BTM0CY or SKT1 BTM1CY 1 tCHECK2 SKT1 BTM0CY or SKT1 BTM1CY 2 tCHECK3 SKT1 BTM0CY or SKT1 BTM1CY 3 SKT1 BTM0CY or SKT1 BTM1CY 4 44 PD17015 As shown in Fig. 10-4, when the BTM0CY and BTM1CY flags are detected at 2 , the timer is updated because the flag is "1". When the flag is detected at 3 , because it is "0", the timer is not updated until it is detected again at 4 . Therefore, the timer is incremented by tCHECK3. Cautions for Using Basic Timers 0 and 1 10.2.5 (1) BTM0CY and BTM1CY flags detection time interval As described in Section 10.2.4, keep the BTM0CY and BTM1CY flags detection time interval shorter than the BTM0CY and BTM1CY flags set time interval. Otherwise, the BTM0CY and BTM1CY flags cannot be set if the time required for process B is longer than the BTM0CY and BTM1CY flags set time interval, as shown in Fig. 10-5. Fig. 10-5 Detection of the BTM0CY and BTM1CY Flags BTM0CY flag set pulse BTM1CY flag set pulse BTM0CY flag BTM1CY flag H L 1 2 3 4 5 1 0 SKT1 BTM0CY or SKT1 BTM1CY SKT1 BTM0CY or SKT1 BTM1CY SKT1 BTM0CY or SKT1 BTM1CY Process A Process B Because the time required for process B is long after the BTM0CY and BTM1CY flags, which is set to "1" at 2 , is detected, the BTM0CY and BTM1CY flags, which is set to "1" at 3 , cannot be detected. (2) Sum of the timer update process time and the BTM0CY and BTM1CY flags detection time interval As explained in (1), the BTM0CY and BTM1CY flags detection time interval must be kept shorter than the BTM0CY and BTM1CY flags set time interval. Even when the BTM0CY and BTM1CY flags detection time interval is short, however, if the timer update process time is long, a CE reset may prevent a normal timer update process. The following conditions must therefore be satisfied. tCHECK + tTIMER < tSET where tCHECK : BTM0CY and BTM1CY flags detection time interval tTIMER : Timer update process time tSET : BTM0CY and BTM1CY flags set time interval The coding that meets these conditions is given below. 45 PD17015 Example Timer update process and BTM0CY flag detection time interval START: Process A BTIMER: ; BR Timer update BR AAA: Process B BR BTIMER BTIMER 1 ; Program address 0000H SKT1 BTM0CY AAA ; Updates the timer if the BTM0CY flag is set to 1. The timing chart for this coding is as follows: H CE pin L H BTM0CY flag set pulse L 1 BTM0CY flag 0 BTM0CY detection time interval tCHECK 1 Timer update process tTIMER A CE reset occurs if this timer update process takes long time. SKT1 BTM0CY 1 SKT1 BTM0CY CE reset 46 PD17015 10.2.6 Cautions for Using Basic Timer 0 (1) Correcting the basic timer 0 at a CE reset The following paragraphs describe an example of correcting the timer at a CE reset. As explained in the example, it is necessary to correct the timer at a CE reset, if the BTM0CY flag is used both to detect a power failure and to control the clock timer. The BTM0CY flag is cleared (0) when the supply voltage is first applied (at power-on reset). It is not set until its contents have been read by an instruction listed in Table 10-1. When the CE pin goes from a low level to a high level, a CE reset occurs in synchronization with the rising edge of the BTM0CY flag set pulse, setting the BTM0CY flag to "1" and making it active. Detecting the state of the BTM0CY flag at a system reset (power-on or CE reset) can therefore check for a power failure. If the flag is "0", it means that a power-on reset has occurred. If it is "1", it means that a CE reset has occurred (power failure detection). In this case, a clock timer must keep operating even at a CE reset. However, reading the BTM0CY flag for power failure detection clears the flag to 0 and makes it impossible to detect the set (1) state of the flag for one cycle. To solve this problem, it is necessary to update the clock timer if an attempt to detect a power failure detects a CE reset. See Section 15.5 for power failure detection. Example Correcting the timer at a CE reset (when the BTM0CY flag is used for both power failure detection and timer update) START : Process A ;1 SKT1 BR BACKUP : ;2 Timer update by 125 ms LOOP: ;3 Process B SKF1 BR BR INITIAL : Process C BR LOOP BTM0CY BACKUP LOOP ; While performing process B, ; tests the BTM0CY flag and updates the timer. ; Timer correction because of backup (CE reset) BTM0CY INITIAL ; Built-in macro ; Checks the BTM0CY flag and branches to INITIAL ; if the flag is "0" (power failure detected). ; Program address 0000H Fig. 10-6 shows the timing chart for the above program. 47 PD17015 Fig. 10-6 Timing Chart 3.0 V 0V H CE L 8 Hz H VDD internal pulse BTM0CY flag set pulse BTM0CY flag Program processing Program instruction Supply voltage applied L H L 1 0 A 1 C 3 B 3 B 3 B 3 B 3 B 3 B 3 B 3 BB 3 3 B A 1 B 3 B 3 B Start at address 0 on a power-on reset Timer incremented Timer incremented Timer incremented Timer incremented Start at address 0 on a CE reset Timer incremented BTM0CY flag detected Point A Point B Timer updated because the BTM0CY flag has been detected to be set (1) Point C Point D Point E As shown in Fig. 10-6, when supply voltage VDD is applied, the 8 Hz internal pulse rises to make the program start at address 0000H. When the BTM0CY flag is detected at point A, the BTM0CY flag appears to be cleared (0) because it is just after power is supplied. Consequently, it is determined that a power failure (power-on reset) has occurred. Then, process C is performed. So, process C is performed to select 100 ms as the BTM0CY flag set pulse. Because the BTM0CY flag is once read-accessed at point A, the BTM0CY flag will be set (1) at intervals of 125 ms. Even when the CE pin goes to a low at point B and goes to a high at point C, the program continues to update the clock while performing process B, unless the clock stop instruction is executed. Because the CE pin goes from a low to a high at point C, a CE reset occurs at point D, where the BTM0CY flag set pulse rises, to start the program at address 0000H. When the BTM0CY flag is detected at point E, it is determined that a backup (CE reset) has occurred, because the flag appears to be set (1). Also, as easily seen from the figure, if the clock is not updated by 125 ms at point E, the clock loses 125 ms every time a CE reset occurs. If process A takes more than 125 ms to detect for a power failure at point E, it is impossible to detect the BTM0CY flag for two cycles. Therefore, process A must be performed within 125 ms. It is necessary, therefore, to detect the BTM0CY flag for power failure detection after the program starts at address 0000H and before the BTM0CY flag is set. 48 PD17015 (2) When the BTM0CY flag is detected simultaneously with a CE reset As described in (1), a CE reset occurs at the same time the BTM0CY flag is set (1). Under this condition, if a read instruction is executed for the BTM0CY flag simultaneously with a CE reset, the read instruction takes preference. Therefore, if a BTM0CY flag read instruction occurs simultaneously with the rising edge of the BTM0CY flag set pulse that occurs after the CE pin goes from a low to a high, a CE reset occurs when the BTM0CY flag is set on the next cycle. This operation is illustrated in Fig. 10-7. Fig. 10-7 Operation That Occurs If a CE Reset Occurs Simultaneously with a BTM0CY Flag Read Instruction H L BTM0CY flag H set pulse L 1 BTM0CY flag 0 CE pin SKT 1 BTM0CY H BTM0CY flag set pulse L 1 BTM0CY flag 0 Instruction SKT1 BTM0CY SKT 1 BTM0CY CE reset 53.3 s If the BTM0CY flag is read during this period, a CE reset is deferred by one cycle. Normally, the program starts at address 000H at this point, but a CE reset does occur because the program to read the BTM0CY flag also happens to run. 49 PD17015 11. PLL FREQUENCY SYNTHESIZER The PLL (Phase Locked Loop) frequency synthesizer is used to lock MF (Medium Frequency), HF (High Frequency) or VHF (Very High Frequency) band frequencies to a fixed frequency using a phase error comparison system. 11.1 GENERAL Fig. 11-1 outlines the PLL frequency synthesizer. A PLL frequency synthesizer can be built by connecting a low pass filter (LPF), voltage controlled oscillator (VCO), and prescaler externally. The PLL frequency synthesizer divides the signal input from the VCOH or VCOL pin using a programmable divider and outputs the phase error with the reference frequency to the EO pin. The PLL frequency synthesizer operates only when the CE pin is high level. When the CE pin is low level, the PLL frequency synthesizer is disabled. For a description of the PLL disabled state, see Section 11.5. Fig. 11-1 PLL Frequency Synthesizer DBF VCOH VCOL Input switching block Programmable divider Phase comparator ( -DET) EO Charge pump Note 75 kHz Reference frequency generator Unlock detection block Low-pass filter (LPF) Note Voltage controlled oscillator (VCO) PLLMD0 flag PLLMD1 flag PLLRFCK0 flag PLLRFCK1 flag PLLUL flag Note External circuit. Remarks 1. PLLRFCK0 and PLLRFCK1 (bits 0 and 1 of PLL mode selection register: see Fig. 11-3): Set the PLL frequency synthesizer reference frequency fr. 2. PLLMD0 and PLLMD1 (bits 2 and 3 of PLL mode selection register: see Fig. 11-3): Set the frequency division method of the PLL frequency synthesizer. 3. PLLUL (bit 0 of PLL unlock flip-flop judge register: see Fig. 11-8): Detects the state of the unlock flip-flop. 50 PD17015 11.2 11.2.1 INPUT SWITCHING BLOCK AND PROGRAMMABLE DIVIDER Configuration Fig. 11-2 shows the configuration of the input switching block and programmable divider. The input switching block consists of the VCOH and VCOL pins and their input amplifiers. The programmable divider consists of a two-modulus prescaler, swallow counter, programmable counter, and division method selection switches. Fig. 11-2 Input Switching Block and Programmable Divider PLLMD0 flag PLLMD1 flag 16 2-4 decoder PLL data register 12 bits MF VHF VCOH HF 2-modulus prescaler 1/16, 1/17 VHF VHF HF 4 bits 4 PSC 12 Swallow counter (4 bits) fN To -DET DBF Programmable counter (12 bits) MF HF VCOL MF PLL disable signal 51 PD17015 11.2.2 Functions The input switching block and programmable divider select the input pin and division method to be used by the PLL frequency synthesizer. Either the VCOH or VCOL pin can be selected as the input pin. The selected pin will have an intermediate potential (about half of VDD). The input to the pin is provided by an AC amplifier. The DC element should be eliminated from the input signal by connecting a capacitor in series with the pin. As the division method, either direct division or pulse swallow can be selected. The programmable divider divides the signal input by means of the selected division method, using the division ratio set by the swallow counter and programmable counter. Table 11-1 lists the division methods and input pins (VCOH and VCOL pins) to be used. The input pin and division method to be used are selected according to the PLLMD0 and PLLMD1 flags of the PLL mode select register. Fig. 11-3 shows the configuration of the PLL mode select register, together with its functions. The division ratio of the programmable divider is set by the PLL data register via data buffers. Section 11.2.3 describes the programmable divider and PLL data register. Table 11-1 Input Pins and Division Methods Division method Pin used Input frequency range (MHz) 0.5 to 8 Input amplitude (Vp-p) 0.2 Possible division ratio Division ratio that can be set in the data buffers 010xH - FFFxH (x: Don't care about low-order 4 bits.) 0100H-FFFFH Direct division (MF) VCOL 16 to 212 - 1 Pulse swallow (HF) Pulse swallow (VHF) VCOL 6 to 55 0.2 256 to 216 - 1 VCOH 40 to 220 0.2 256 to 216 - 1 0100H-FFFFH 52 PD17015 Fig. 11-3 Configuration and Functions of the PLL Mode Select Register Flag symbol Name b3 P L L M D 1 b2 P L L M D 0 b1 P L L R F C K 1 b0 P L L R F C K 0 Address Read/write PLL mode select register 6BH R/W Sets reference frequency fr of the PLL frequency synthesizer.Note 0 0 1 1 0 1 0 1 1 kHz 3 kHz 5 kHz 25 kHz Sets the division method used by the PLL frequency synthesizer. 0 0 1 1 0 1 0 1 Disables pins VCOL and VCOH Selects direct division (VCOL pin, MF mode). Selects pulse swallow (VCOH pin, VHF mode). Selects pulse swallow (VCOL pin, HF mode). Upon reset Power-on Clock-stop CE 0 0 0 0 0 0 0 0 Hold Note For details of the reference frequency, see Section 11.3. Items (1) to (4), below, outline the division methods: (1) Direct division (MF) The VCOL pin is used. The VCOH pin enters the floating state. In direct division, the signal input is divided according to the programmable counter only. (2) Pulse swallow (HF) The VCOL pin is used. The VCOH pin enters the floating state. When using pulse swallow, the signal input is divided according to the settings of the swallow counter and programmable counter. (3) Pulse swallow (VHF) The VCOH pin is used. The VCOL pin enters the floating state. When using pulse swallow, the signal input is divided according to the settings of the swallow counter and programmable counter. 53 PD17015 (4) VCOL and VCOH pins disabled The VCOL and VCOH pins enter the floating state. In this state, the phase comparator and reference frequency generator stop the output, and the charging pump sets the EO output pin to the floating state. This operation is the same as that performed in the PLL disable state, described in Section 11.5. 11.2.3 Programmable Divider and PLL Data Register The programmable divider divides the signal input from the VCOH or VCOL pin, using the division ratio set by the swallow counter and programmable counter. The swallow counter and program counter are 4-bit and 12-bit binary down-counters, respectively. The division ratios for the swallow counter and program counter are set in the PLL data register (PLLR: peripheral address 41H) via data buffers. Data is written to and read from the PLL data register by the PUT PLLR, DBF and GET DBF, PLLR instructions. The division ratio is referred to as the N value. For details of setting division ratio (N value) for each division method, see Section 11.6. (1) PLL data register and data buffer Fig. 11-4 shows the relationship between the PLL data register and data buffers. In direct division, the high-order 12 bits are valid. When pulse swallow is being used, all 16 bits are valid. In direct division, the above 12 bits are set in the programmable counter. When pulse swallow is being used, the high-order 12 bits are set in the programmable counter while the loworder four bits are set in the swallow counter. (2) Relationship between division value N of the programmable divider and the divided output frequency The following expressions indicate the relationship between value N, set in the PLL data register, and frequency fN of the signal output divided by the programmable divider: (a) Direct division (MF) fIN N fN = (N: 12 bits) (b) Pulse swallow (HF, VHF) fIN N fN = (N: 16 bits) 54 PD17015 Fig. 11-4 Relationship between the PLL Data Register and Data Buffers Name Symbol Address Bit Data b3 DBF3 0CH b2 b1 b0 b3 DBF2 0DH b2 b1 Data buffer DBF1 0EH b0 b3 b2 b1 b0 b3 DBF0 0FH b2 b1 b0 Transfer data GET instruction allowed 16 PUT instruction allowed Peripheral register Name PLL data register b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Symbol Peripheral address Peripheral hardware Valid data PLLR 41H PLL frequency synthesizer Sets the division ratio of the PLL frequency synthesizer. 0 | 15 (00FH) 16 (010H) Direct division | x | 212-1 (FFFH) 0 | 255 (00FFH) 256 (0100H) Pulse swallow | x | 216-1 (FFFH) Division ratio N:N = x Not to be set Don't care Don't care Division ratio N:N = x Don't care Don't care Don't care Not to be set 55 PD17015 11.3 REFERENCE FREQUENCY GENERATOR Fig. 11-5 shows the configuration of the reference frequency generator. The reference frequency generator generates the PLL frequency synthesizer reference frequency "fr" by dividing the 75-MHz signal of a crystal oscillator. The reference frequency fr can be selected from among 1 kHz, 3 kHz, 5 kHz, and 25 kHz. The reference frequency fr is selected with the PLLRFCK0 and PLLRFCK1 flags of the PLL mode selection register (see Fig. 11-3). Fig. 11-5 Reference Frequency Generator PLLRFCK0 flag PLLRFCK1 flag 2-4 decoder Frequency divider 1 kHz 3 kHz fr 5 kHz 25 kHz Selector To -DET 75 kHz 56 PD17015 11.4 11.4.1 PHASE COMPARATOR (-DET), CHARGE PUMP AND UNLOCK DETECTION BLOCK Configuration of Phase Comparator, Charge Pump and Unlock Detection Block Fig. 11-6 shows the configuration of the phase comparator, charge pump and unlock detection block. The phase comparator compares the phase of the divided frequency (fN) signal output from the programmable divider and that of the reference frequency (fr) signal output from the reference frequency generator and outputs an up request signal (UP) or down request signal (DW). The charge pump outputs the output of the phase comparator from the error out pin (EO pin). The unlock detection block detects the PLL frequency synthesizer unlocked state from UP and DW. Sections 11.4.2 to 11.4.4 describe the operation of the phase comparator, charge pump, and unlock detection block. Fig. 11-6 Phase Comparator, Charge Pump and Unlock Detection Block PLLUL flag Reference frequency generator fr UP Unlock detection block Phase comparator ( -DET) fN DW Charge pump Programmable divider EO PLL disable signal 57 PD17015 11.4.2 Phase Comparator Functions As shown in Fig. 11-6, the phase comparator compares the phase of the programmable divider divided (fN) output and that of the reference frequency (fr) signal and outputs an up request signal or down request signal. That is, if divided frequency "fN" is lower than reference frequency "fr", an up request signal is output, and if divided frequency "fN" is higher than reference signal "fr", a down request signal is output. Fig. 11-7 shows the relationship among the reference frequency fr, division frequency fN, up request signal, and down request signal. In the PLL disabled state, neither an up request signal nor a down request signal is output. The up request and down request signals are input to the charge pump and unlock detection block. Fig. 11-7 fr, fN, UP, and DW Signal Relationship (a) When fN phase lags fr phase fr fN UP DW (b) When fN phase leads fr phase fr fN UP DW (c) When fN and fr are same phase fr fN UP DW (d) When fN frequency lower than fr frequency fr fN UP DW 11.4.3 Charge Pump As shown in Fig. 11-6, the charge pump outputs the up request signal or down request signal sent from the phase comparator, from the error out pin (EO pin). Error output pin output, division frequency fN, and reference frequency fr have the following relation: When reference frequency fr > division frequency fN: Low level output When reference frequency fr < division frequency fN: High level output When reference frequency fr = division frequency fN: Floating 58 PD17015 11.4.4 Functions of Unlock Detection Block As shown in Fig. 11-6, the unlock detection block detects the PLL frequency synthesizer unlocked state from the phase comparator up request and down request signals. That is, since the up request signal or down request signal outputs low level while the PLL frequency synthesizer is in the unlocked state, the unlocked state can be detected by monitoring this low level signal. When the PLL frequency synthesizer is in the unlocked state, the unlock flip-flop is set (1). The state of the unlock flip-flop is detected by the PLLUL flag of PLL unlock flip-flop judge register (see Fig. 11-8). The unlock flip-flop is set at the period of the reference frequency fr selected at the time. The contents of the PLL unlock flip-flop judge register are read with instructions shown in Table 11-2 and reset (Read & Reset). The unlock flip-flop must be detected at a period longer than reference frequency fr period 1/fr. Fig. 11-8 Configuration and Functions of PLL Unlock Flip-Flop Judge Register Flag symbol Register b3 b2 b1 b0 P L L U L Address Read/write PLL unlock flip-flop judge register 0 0 0 6DH Read & Reset Detects the state of the unlock flip-flop. 0 1 Unlock flip-flop = 0 : PLL locked Unlock flip-flop = 1 : PLL unlocked Fixed to 0. Upon reset Power-on Clock stop CE rest 0 0 0 * Hold Hold * Undefined 59 PD17015 Table 11-2 Instructions Which Reset the PLL Unlock Flip-Flop Judge Register Mnemonic ADD ADDC SUB SUBC AND OR XOR SKE SKEG SKLT SKNE Operand Mnemonic ADD ADDC SUB SUBC Operand m, #n4 AND OR XOR LD SKT SKF MOV r, m m, #n @r, m m, @rNote Note When the low address of m is 6H, and 0DH is written into r. Remark m = 6DH 60 PD17015 11.5 PLL DISABLED STATE The PLL frequency synthesizer is disabled while the CE pin (pin 13) is low level. The PLL frequency synthesizer is also disabled when VCOH/VCOL pin disabled is selected by the PLL mode selection register, even if the CE pin is set to high level. Table 11-3 shows the state of each block at PLL disabled. Since the PLL mode selection register is not initialized (previous state is held) at CE reset, it is reset to its previous state when the CE pin rises to high level after dropping to low level and PLL disabled is set. Therefore, when PLL disabled must be set at CE reset, the PLL reference clock selection register must be initialized by program. At power-on reset, PLL disabled is set. Table 11-3 Operation of Each Block at PLL Disabled Condition Block VCOL/VCOH pin Programmable divider Reference frequency generator CE pin = low level (PLL disabled) CE pin = high level (PLLMD = 0000B: VCOH/VCOL pin disabled) Floating Frequency division stopped Output stopped Phase comparator Charge pump EO pin floated 11.6 PLL FREQUENCY SYNTHESIZER USE To control the PLL frequency synthesizer, the following data is necessary: (1) Frequency division method : Direct division (MF), pulse swallow (HF, VHF) (2) Pins to be used (3) Reference frequency (4) Division value : VCOL and VCOH pins : fr :N Sections 11.6.1 to 11.6.3 describe the PLL data setting method for each division method (MF, HF, or VHF). 11.6.1 Direct Division Method (MF) (1) Selecting the division method to be used The direct division method is selected by setting the PLLMD0 or PLLMD1 flag of the PLL mode selection register. (2) Pins to be used The VCOL pin becomes available when the direct division method is selected. (3) Reference frequency fr setting The reference frequency is set by the PLLRFCK0 or PLLRFCK1 flag of the PLL mode selection register. 61 PD17015 (4) Division value N computation method Division value N is computed as follows: fVCOL fr fVCOL fr (5) PLL data setting example The method of setting the data to receive a MF band broadcast station is shown below. Receiving frequency Reference frequency : 1422 kHz (MW band) : 3 kHz : VCOL pin input frequency : Reference frequency N= Intermediate frequency : +450 kHz Division value N is: fVCOL fr 1422 + 450 3 N= = = 624 (decimal) = 270H (hexadecimal) Data is written to the PLL data register and PLL mode selection register as follows: PLLR 0010 2 0111 7 0000 0 Any value PLLMD 0101 MF, 3 kHz 11.6.2 Pulse Swallow Method (HF) (1) Selection of the division method The pulse swallow method is selected by the PLLMD0 or PLLMD1 flag of the PLL mode selection register. (2) Pins to be used The VCOL pin becomes available when the pulse swallow method is selected. (3) Reference frequency fr setting The reference frequency is set with the PLLRFCK0 or PLLRFCK1 flag of the PLL mode selection register. (4) Division value N computation Division value N is computed as follows: fVCOL fr fVCOL fr : VCOL pin input frequency : Reference frequency N= 62 PD17015 (5) PLL data setting example The data to be set to receive a SW band broadcast station is shown below. Receiving frequency Reference frequency : 25.50 MHz (SW band) : 5 kHz Intermediate frequency : +450 kHz Division value N is: fVCOL fr 25500 + 450 5 N= = = 5190 (decimal) = 1446H (hexadecimal) Data is written into the PLL data and PLL mode selection registers as follows: PLLR 0001 1 0100 4 0100 4 0110 6 PLLMD 1110 HF, 5 kHz 11.6.3 Pulse Swallow Method (VHF) (1) Selection of division method The pulse swallow method is selected by setting the PLLMD0 or PLLMD1 flag of the PLL mode selection register. (2) Pins to be used The VCOH pin becomes available when the pulse swallow method is selected. (3) Reference frequency fr setting The reference frequency is set by the PLLRFCK0 or PLLRFCK1 flag of the PLL mode selection register. (4) Division value N computation method Division value N is computed as follows: fVCOH fr fVCOH fr : VCOH pin input frequency : Reference frequency N= 63 PD17015 (5) PLL data setting example The data to be set to receive an FM band broadcast station is shown below. Receiving frequency Reference frequency : 100.0 MHz (FM band) : 25 kHz Intermediate frequency : +10.7 kHz Division value N is: fVCOH fr 100.0 + 10.7 0.025 N= = = 4428 (decimal) = 114CH (hexadecimal) Data is written into the PLL data and PLL mode selection registers as follows: PLLR 0001 1 0001 1 0100 4 1100 C PLLMD 1011 VHF, 25 kHz 11.7 11.7.1 STATE AT RESET At Power-On Reset Since the PLL mode selection register is initialized to 0000B, the PLL disabled state is set. 11.7.2 At Clock-Stop The PLL disabled state is set at the time the CE pin drops to low level. 11.7.3 At CE Reset (1) CE reset caused by clock stop Since clock-stop initializes the PLL mode selection register to 0000B, the PLL disabled state is set. (2) CE reset when clock not stopped Since the PLL mode selection register retains its previous state, the previous state is set when the CE pin rises to high level. 11.7.4 During the Halt State If the CE pin is high level, the set state is held. 64 PD17015 12. BEEP 12.1 CONFIGURATION AND FUNCTIONS Fig. 12-1 shows an overview of BEEP. A 3-kHz clock is output from the P0D0/BEEP pin. According to the settings of the BEEP0SEL flag of the LCD enable register, the output switching block controls whether the P0D0/BEEP pin functions as a general-purpose output port or as a BEEP output pin. The clock generation block generates the 3-kHz clock to be output to the BEEP pin. Fig. 12-2 shows the configuration and functions of the LCD enable register. Fig. 12-1 Overview of BEEP BEEP0SEL flag P0D0/BEEP Output switching block 3 kHz Clock generation block Fig. 12-2 Configuration and Functions of the LCD Enable Register Flag symbol Name Address b3 L C D E N b2 B E E P 0 S E L b1 P 0 A B I O 1 b0 P 0 A B I O 0 4 Read/write LCD enable register 6AH R/W Sets the function of the P0D0/BEEP pin. 0 1 Uses the P0D0/BEEP pins as a general-purpose output port. Uses the P0D0/BEEP pin as a BEEP output pin. Upon reset Power-on Clock-Stop CE 0 0 0 0 Hold 0 0 0 0 65 PD17015 12.2 12.2.1 STATE AT RESET At Power-On Reset The BEEP0SEL flag is reset. Consequently, the P0D0/BEEP pin is used as a general-purpose output port. Because the latch value for the output port is not defined, the port outputs undefined data. 12.2.2 At Clock-Stop Reset The BEEP0SEL flag is reset. Consequently, the P0D0/BEEP pin is used as a general-purpose output port. Because the latch value is not defined for the output port, the port outputs undefined data. 12.2.3 At CE Reset The P0D0/BEEP pin holds the previous output state. 12.2.4 During the Halt State The P0D0/BEEP pin holds the previous output state. 66 PD17015 13. LCD CONTROLLER/DRIVER The LCD (liquid crystal display) controller/driver, in combination with the segment signal output, controls an LCD display of up to 36 segments. 13.1 Overview Fig. 13-1 shows an overview of the LCD controller/driver. The LCD controller/driver controls a display consisting of up to 36 segments by using both the common signal output (COM0 to COM3 pins) and segment signal output (LCD0 to LCD8 pins). The driving method features a 1/4 duty cycle and 1/2 bias, a frame frequency of 150 Hz, and a driving voltage of VDD - VLCD0. Fig. 13-1 Overview of LCD Controller/Driver LCD0 pin Segment signal output timing control block LCD8 pin LCD segment register (data memory space) COM0 pin COM3 pin Common signal output timing control block Basic clock for timing control LCDEN flag VLCD0 pin VLCD1 pin CAP0 pin CAP1 pin LCD driving voltage generation block Remark LCDEN (bit 3 of the LCD enable register; see Fig. 13-6) turns the entire LCD display on or off. 67 PD17015 13.2 LCD DRIVING VOLTAGE GENERATION BLOCK The LCD driving voltage generation block generates the voltage needed to drive the LCD. An external doubler of the PD17015 supplies the LCD drive voltage. To configure the doubler, connect capacitors to the VLCD0, CAP0, CAP1, and VLCD1 pins. 5 Fig. 13-2 shows a sample doubler configuration. To use a voltage of 3.0 V (TYP.), connect capacitors as shown in Fig. 13-2. 5 Fig. 13-2 Sample Doubler Configuration C1 VLCD0 (36) CAP0 (35) C3 CAP1 (34) VLCD1 (33) C2 C1 = C2 = 0.1 F C3 = 0.01 F Remark Pin numbers are enclosed in parentheses. Note that the LCD driving voltage (VLCD) output by the doubler depends on the values of C1, C2, and C3. 68 PD17015 13.3 LCD SEGMENT REGISTER The LCD segment register sets the data indicating the LCD segments to be turned on or off. Fig. 13-3 shows the configuration and position of the LCD segment register in data memory. The LCD segment register exists in data memory and can, therefore, be controlled by all data memory manipulation instructions. One nibble of the LCD segment register sets the display data (turn-on/off data) for four segments. When a bit of the segment register is set to 1, the corresponding LCD segment is lit. When the bit is set to 0, the segment is not lit. Fig. 13-4 indicates the relationship between the LCD segment register and LCD segments, together with display examples. Fig. 13-3 Configuration of LCD Segment Register in Data Memory Column address 0 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 8 9 A B CDE F Row address Data memory LCD segment register System register LCD segment register Address Symbol 61H LCDD8 62H LCDD7 63H LCDD6 64H LCDD5 65H LCDD4 66H LCDD3 67H LCDD2 68H LCDD1 69H LCDD0 LCDD8 b3 b2 b1 b0 69 70 Address Symbol Bit Display segment Fig. 13-4 Relationship Between LCD Segment Register and LCD Segments, and Examples of Display LCD segment register 61H LCDD8 62H LCDD7 63H LCDD6 64H LCDD5 65H LCDD4 66H LCDD3 67H LCDD2 68H LCDD1 69H LCDD0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 a b c d a b c d e f g h a b c d e f g h ab c d e f g h a b c d e f g h COM3 pin a a e a e a e a e COM2 pin b b f b f b f b f c COM1 pin c g c g c g c g d COM0 pin d h d h d h d h LCD8 pin a b c d LCD7 pin a f e d g LCD6 pin LCD5 pin a LCD4 pin LCD3 pin a LCD2 pin LCD1 pin a LCD0 pin b c h f e g b c f e h g b c f e h g b c d d d h PD17015 PD17015 13.4 TIMING CONTROL BLOCKS FOR OUTPUTTING COMMON SIGNAL AND SEGMENT SIGNAL Fig. 13-5 shows the configuration of the timing control blocks for outputting the common signal and segment signal. The common signal output timing control block controls the timing of the common signal output on pins COM0 to COM3. The segment signal output timing control block controls the timing of the segment signal output on pins LCD0 to LCD8. The common signal and segment signal are output when the LCDEN flag of the LCD enable register is set to 1. Setting the LCDEN flag to 0 turns off the entire LCD display. (See Fig. 13-6.) When the LCD display is turned off, the signals output from pins COM0 to COM3 and pins LCD0 to LCD8 are held low. Fig. 13-5 Configuration of Timing Control Blocks for Outputting Common Signal and Segment Signal b0 LCD0 | Segment signal LCDD0 | LCDD8 LCD8 Segment signal output timing control block b1 b2 b3 Basic clock for timing control LCDEN flag COM0 | Common signal COM3 Common signal output timing control block Fig. 13-6 Configuration and Functions of LCD Enable Register Flag symbol Name b3 L C D E N b2 B E E P 0 S E L b1 P 0 A B I O 1 b0 P 0 A B I O 0 Address Read/write LCD enable register 6AH R/W Turns the entire LCD display on or off. 0 1 Turns the display off. (The output from all the segment and common pins is held low.) Turns the display on. Upon reset Power-on Clock-stop CE 0 0 0 0 0 0 0 0 Hold 71 PD17015 13.5 5 COMMON SIGNAL AND SEGMENT SIGNAL OUTPUT WAVEFORMS Fig. 13-7 shows sample waveforms for common signal and segment signal output. The PD17015 outputs signals at a frame frequency of 62.5 Hz when driving at a 1/4 duty cycle and 1/2 bias (voltage averaging method). The common signals output from pins COM0 to COM3 have a relative phase difference of 1/8 and three voltage levels (VLCD0, VLCD1, and VDD). The middle voltage level VLCD1 of the output common signals increases or decreases by 1/2 VDD. This display method is referred to as the 1/2-bias driving method. Each segment signal output pin outputs the segment signal with two voltage levels (0 and VDD) and phases corresponding to the display segments. As shown in Fig. 13-7, a single segment pin is used for four display segments (A, B, C, and D). Each segment pin can output 16 different combinations of phases, corresponding to the turning on and off of the display segments. A display segment is lit when the voltage difference between the common signal and segment signal is VDD. 5 The display segments are turned on in 1/4 duty cycles at a frequency of 62.5 Hz. This is referred to as the 1/4-duty display method. The frequency is referred to as the frame frequency. 72 PD17015 Fig. 13-7 Common Signal and Segment Signal Output Waveforms COM0 pin COM1 pin A B COM2 pin COM3 pin C D Segment signal output pin (LCDn pin) Common signal Single frame (6.7 ms) 1.7 ms COM0 pin VLCD1 VLCD0 GND VLCD1 VLCD0 GND VLCD1 COM2 pin VLCD0 GND VLCD1 COM3 pin VLCD0 GND COM1 pin Segment signal (examples) A, B, C, and D turned off VLCD1 LCDn pin A, B, C, and D turned on VLCD1 LCDn pin GND A, B, and C turned on; D turned off VLCD1 LCDn pin GND GND 73 PD17015 13.6 USING THE LCD CONTROLLER/DRIVER Fig. 13-8 shows an example of LCD panel connection. The following sample program turns on the 7-segment display with the LCD0 and LCD1 pins. Example WORK PMNO CH ;LCDDATA: ; ; ; ; ; ; ; ; ; ; ; DW DW DW DW DW DW DW DW DW DW abcdefg- 0000000011111100B 0000000001100000B 0000000011011010B 0000000011110010B 0000000001100110B 0000000010110110B 0000000010111110B 0000000011100100B 0000000011111110B 0000000011110110B SKE BR MOV MOV LCD1: SKE BR MOV MOV LCD2: SKE BR MOV MOV LCD3: SKE BR MOV MOV WORK0, #3 LCD4 DBF0, #2 DBF1, #0FH WORK0, #2 LCD3 DBF0, #0AH DBF1, #0DH WORK0, #1 LCD2 DBF0, #0 DBF1, #6 WORK0, #0 LCD1 DBF0, #0CH DBF1, #0FH ; 0FCH0 ; 60H1 ; 0DAH2 ; 0F2H3 ; 66H4 ; 0B6H5 ; 0BEH6 ; 0E4H7 ; 0FEH8 ; 0F6H9 MEM MEM FLG 0.00H 0.01H LCDD0.1 ; Work area ; Storage area of preset memory number ; Defines the low-order one bit of LCDD0 as the symbol CH display. ; Display segment data CNG_LCD_DAT: 74 PD17015 LCD4: SKE BR MOV MOV LCD5: SKE BR MOV MOV LCD6: SKE BR MOV MOV LCD7: SKE BR MOV MOV LCD8: SKE BR MOV MOV LCD9: SKE RET MOV MOV RET PRESET_CH: LD CALL ST ST SET1 SET1 END WORK, PMNO CNG_LCD_DAT LCDD0, DBF0 LCDD1, DBF1 CH LCDEN ; Display turned on DBF0, #6 DBF1, #0FH WORK0, #9 WORK0, #8 LCD9 DBF0, #0EH DBF1, #0FH WORK0, #7 LCD8 DBF0, #4 DBF1, #0EH WORK0, #6 LCD7 DBF0, #0EH DBF1, #0BH WORK0, #5 LCD6 DBF0, #6 DBF1, #0BH WORK0, #4 LCD5 DBF0, #6 DBF1, #6 75 PD17015 Fig. 13-8 Example of LCD Panel Connection TV FM AM PM f a b g e d c e f a b g c d e f a b g c d e f a b g c d h h ch LCD8 COM2 COM0 COM3 COM1 LCD6 LCD7 LCD4 LCD5 LCD2 LCD3 LCD0 LCD1 Relationship between the segment and common pins and the display segments on the LCD panel Segment signal L C D 8 L C D 7 L C D 6 L C D 5 L C D 4 L C D 3 L C D 2 L C D 1 L C D 0 Common Pin No. 20 21 22 23 24 25 26 27 28 signal COM3 COM2 COM1 COM0 29 30 31 32 TV FM AM a b c e f g : a b c d e f g h a b c d e f g h a b c d e f g ch PM d 13.7 13.7.1 STATE AT RESET At Power-On Reset and Clock-Stop Reset The signals output from the LCD0 to LCD8 pins go low. The signals output from pins COM0 to COM3 also go low. Consequently, the LCD display is turned off. 13.7.2 AT CE Reset and During the Halt State Segment signals are output from pins LCD0 to LCD8. Common signals are output from pins COM0 to COM3. 76 PD17015 14. STANDBY The standby function is used to reduce the supply current during back-up. 14.1 STANDBY FUNCTIONS Fig. 14-1 outlines the standby block. The standby block reduces the device current drain by stopping some, or all, operations of the device. The standby block has the following three functions. These functions can be used to suit the application. 1 2 3 Halt function Clock-stop function Device operation control by CE pin The halt function reduces the device current drain by stopping CPU operation with a "HALT h" instruction. The clock-stop function reduces the device current drain by stopping the oscillation circuit with a "STOP s" instruction. Since the CE pin is used to control operation of the image display controller (IDC) and PLL frequency synthesizer and to reset the device, its operation control function is said to be a standby function. 77 PD17015 Fig. 14-1 Standby Block Halt block BTM0CY Halt control circuit (HALT h) P0B0 P0B1 P0B2 Input latch CPU Program counter Instruction decoder Clock stop block CE flag ALU System register CE Clock-stop control circuit (STOP s) XOUT XIN Internal clock Peripheral control register Remark CE (bit 0 of CE pin level judge register: see Fig. 14-8). Detects the status of the CE pin. 78 PD17015 14.2 14.2.1 HALT FUNCTION General The halt function stops the CPU clock by executing a "HALT h" instruction. When a "HALT h" instruction is executed, the program halts and remains stopped until the halt state is released. In the halt state, the device current drain is reduced by the amount of the CPU operating current. The halt state is released by key input or basic timer 0. The release conditions are specified with the "h" operand of the HALT h instruction. The "HALT h" instruction is valid regardless of the CE pin input level. 14.2.2 Halt State In the halt state, all operations of the CPU are stopped. That is, the "HALT h" instruction stops program execution. However, the peripheral hardware remains in the state set before the "HALT h" is executed. For an operation description of each hardware device, see Section 14.4. 14.2.3 Halt Release Conditions Fig. 14-2 shows the halt release conditions. The halt release conditions are set with the 4-bit data specified by the "h" operand of the "HALT h" instruction. The halt state is released when the condition set to 1 at the "h" operand is satisfied. When the halt state is released, the program is executed from the instruction after the "HALT h" instruction. When multiple release conditions are set, the halt state is released if even one of the set conditions is satisfied. When reset (power-on reset or CE reset) is applied to the device, the halt state is released and the reset operations are performed. When 0000B is set at halt release condition "h", no halt condition is set. If reset (power-on reset or CE reset) is applied to the device at this time, the halt state is released. Fig. 14-2 Halt Release Conditions HALT h (4 bits) Operand b3 b2 b1 b0 0 : Do not release halt state even if condition satisfied. 1 : Release halt state when condition satisfied. Sets the halt state release conditions. Release when a high-level signal is input to port 0B (halt release by the key input). Release when the BTM0CY flag is set (1) (halt release by the basic timer 0). Undefined (Fix it to 0.) 79 PD17015 14.2.4 Halt Release by Key Input Halt release by key input is set by "HALT 0001B" instruction. When the halt release by key input is set, the halt state is released when high level is input at any one of the 0B port lines (P0B2 to P0B0 pins) Each 0B port pin has a built-in pull-down resistor. (1) When general-purpose output port is made key source P0B2 Latch P0B1 Switch A P0B0 General-purpose output port Execute a "HALT 0001B" instruction after the key source signal general-purpose output port is made high level. Note that if an alternate switch like switch A in the figure above is used, while switch A is closed, high level is applied to the P0B0 pin and the halt state is immediately released. (2) When halt released by other microcomputer, etc. Output port P0B2 Latch P0B1 Microcomputer, etc. P0B0 General-purpose output port Halt can be released by another microcomputer, etc. as shown in the figure above. 80 PD17015 14.2.5 Halt Release by Basic Timer 0 Halt release by basic timer 0 is set by the "HALT 0010B" instruction. When halt release by basic timer 0 is set, the halt state is released simultaneously with setting (1) of the carry flip-flop of basic timer 0. The carry flip-flop of basic timer 0 corresponds to the BTM0CY flag, and is set at intervals of 125 ms. The halt state can be released at a fixed cycle. Example Program that releases the halt state every 125 ms and executes process A every second. M1 HLTTMR LOOP: HALT SKT1 BR ADD SKT1 BR HLTTMR BTM0CY LOOP M1, #0010B CY LOOP ; Sets the condition of release caused by basic timer 0 ; and sets to the halt state. ; Built-in macro ; If BTM0CY flag is not set, branches to LOOP. ; Adds 0010B to contents of M1. ; Built-in macro ; If a carry is generated, executes process A. MEM DAT 0.10H 0010B ; 1 second counter ; Symbol definition Process A BR LOOP 81 PD17015 14.2.6 When Two Release Conditions Set Simultaneously When two halt release conditions are set, the halt state is released if even one of the set release conditions is satisfied. The following example indicates how to judge two release conditions when they are satisfied simultaneously. Example Judging between two release conditions when they are satisfied simultaneously HLTBTMR HLTKEY START: SET3 BTMRUP: Process A RET KEYDEC: Process B RET LOOP: HALT SKF1 CALL SKF3 CALL BR HLTBTMR OR HLTKEY BTM0CY BTMRUP P0B2, P0B1, P0B0 KEYDEC LOOP ; Sets halt release conditions to basic ; timer 0 or key input. ; Detects BTM0CY flag ; If set, executes timer carry processing. ; Key input latch processing ; If latched, executes key input processing P0C2, P0C1, P0C0 ; Outputs key source signal. DAT DAT 0010B 0001B 82 PD17015 14.3 CLOCK-STOP FUNCTION The clock-stop function stops the 75-kHz crystal oscillation circuit (clock stopped state) by executing a "STOP s" instruction. The supply current is reduced by up to 3 A. Specify "0000B" at operand "s" of the "STOP s" instruction. The "STOP s" instruction is valid only when the CE pin is low level. If a "STOP s" instruction is executed while the CE pin is high level, it is executed as a "NOP" instruction. Always execute a "STOP s" instruction when the CE pin is low level. The clock-stop state is released by raising the CE pin from low level to high level (CE reset). 14.3.1 Clock-Stop State Since the crystal oscillation circuit is stopped in the clock-stop state, operation of the CPU, peripheral hardware, and other devices is stopped. For a description of operation of the CPU and each item of peripheral hardware, see Section 14.4. 14.3.2 Clock-Stop State Release The clock-stop state can be released with the two methods described below. For both methods, after the clockstop state is released, the program starts from address 0000H. 1 2 Raising the CE pin from low level to high level (CE reset) Dropping VDD to 1.8 V or less, then raising it to 1.8 V or more (TA = -10 to +50 C). Caution The power-on clear voltage varies with the CPU operating temperature. For details, see Section 15.2. 14.3.3 Clock-Stop Release by CE Reset Fig. 14-3 shows the clock-stop release by CE reset. 83 PD17015 Fig. 14-3 Clock-Stop Release by CE Reset 3.0 V VDD 0V H CE pin L H XOUT pin L Approx. 125 ms STOP s instruction Program starts at address 0 (CE reset) 3.0 V VDD 0V H CE pin L H XOUT pin L If a clock-stop instruction is not used, operation is as follows: 0-tSET Program starts at address 0 (CE reset) CE reset is applied in synchronization with the setting of the BTM0CY flag after the CE pin has been raised to high level. 14.3.4 Clock-Stop Release by Power-On Reset Fig. 14-4 shows the clock-stop release by power-on reset. If the clock-stop state is released by power-on reset, the power failure detection circuit operates. Fig. 14-4 Clock-Stop Release by Power-On Reset (TA = -10 to +50 C) 3.0 V VDD 0V H CE pin L H XOUT pin L Approx. 125 ms STOP s instruction Program starts at address 0 (power-on reset) 1.8 V If a clock-stop instruction is not used, operation is as follows: 3.0 V VDD 0V H CE pin L H XOUT pin L Approx. 125 ms Oscillation stopped Program starts at address 0 (power-on reset) 1.8 V 84 PD17015 14.3.5 Cautions When Using Clock-Stop Instruction The clock-stop instruction (STOP s instruction) is valid only when the CE pin is low level. The program must take into account processing when the CE pin is raised unexpectedly to high level. The description is based on the following example. Example XTAL CEJDG: ;1 SKF1 BR CE MAIN ; Built-in Macro ; Detects the CE pin input level. ; If CE = high level, branches to main processing. ; CE = low level processing Process A ;2 STOP ; 3 DAT 0000B ; Clock-stop condition symbol definition XTAL $-1 ; Clock-stop BR MAIN: Main processing BR CEJDG In the example above, the state of the CE pin is detected at 1 . If the CE pin is low level, after process A is executed, the clock-stop instruction "STOP XTAL" of 2 is executed. However, if the CE pin becomes high level while the "STOP XTAL" instruction of 2 is being executed as shown in the figure below, the "STOP XTAL" instruction operates as a no operation instruction (NOP). If the branch instruction "BR $-1" of 3 does not exit, the program returns to main processing and erroneous operational occurs. Therefore, a branch instruction like 3 must be inserted in the program, or the program must be written so that erroneous operational does not occur even if it returns to main processing. When a branch instruction like 3 is used, CE reset is applied in synchronization with the next setting of the BTM0CY flag, even if the CE pin remains at high level. 3.0 V VDD 0V H CE pin L Main processing Process A 1 2 STOP XTAL The STOP XTAL becomes a NOP instruction because the CE pin is high level. 1 1 CE pin detection The program starts from address 0 in synchronization with setting of the BTM0CY flag. (CE reset) 85 PD17015 14.4 DEVICE OPERATION IN THE HALT AND CLOCK-STOP STATES Table 14-1 shows the operation of the CPU and peripheral hardware in the halt state and clock-stop state. In the halt state, all the peripheral hardware units continue to operate normally except that they stop executing instructions. In the clock-stop state, all the peripheral hardware units stop operating. In the halt state, the peripheral control register that controls the operating state of the peripheral hardware operates normally (not initialized). However, when a clock-stop instruction is executed, it is initialized to the specified value. In short, in the halt state, the operation set in the peripheral control register continues and in the clock-stop state, the operating state is determined in accordance with the initialized peripheral control register value. For the peripheral control register value in the clock-stop state, see the relevant items. A sample program is shown below. Example Program that sets the P0A1 and P0A0 pins as output ports and which performs LCD display HLTBTMR XTAL INITFLG ;1 SET2 LCDDATA : ;2 Process B ;3 SET1 ; 4 DAT DAT 0001B 0000B ; Symbol definition P0ABIO1, P0ABIO0 P0A1, P0A0 LCDEN ; LCD display on HALT ;5 STOP HLTKEY XTAL In the example, 1 outputs high level from the P0A1 and P0A0 pins, 2 sets the display data for the LCD segment register, and 3 turns the LCD display on. When the HALT instruction is executed at when a key input is accepted. If the STOP instruction of ( is executed instead of the HALT instruction of register set at 1 , 2 and purpose input ports. 3 4 4 , LCD display continues turning on, and the halt state is released , all the flags of the peripheral control are initialized. LCD display is terminated and P0A1 and P0A0 pins are made general- 86 PD17015 Table 14-1 Device Operation in Halt State and Clock-Stop State State Peripheral hardware CE pin: High level At halt Program counter Stopped at HALT instruction address. At clock-stop CE pin: Low level At halt Stopped at HALT instruction address. At clock-stop Initialized to 0000H and stopped. InitializedNote 1 Held Held Held InitializedNote 2 STOP instruction invalid (NOP) Normal operation Disabled Operation stopped Normal operation Normal operation Input port Input port Held System register Peripheral hardware register Peripheral control register Basic timer PLL frequency synthesizer BEEP LCD controller/driver General-purpose I/O port General-purpose input port General-purpose output port Notes 1. For the value that is initialized, see Chapter 5. 2. For the value that is initialized, see each section. 14.5 PIN PROCESSING CAUTIONS IN HALT STATE AND CLOCK-STOP STATE The halt state is used to reduce the supply current when only the clock is operating. The clock-stop function is used to reduce the supply current for holding only the data memory. Consequently, the supply current must be reduced as much as possible in the halt and clock-stop states. The supply current depends on the state of each pin and the cautions shown in Table 14-2 must be observed. 87 PD17015 Table 14-2 State of Each Pin and Cautions in Halt and Clock-Stop States State of each pin and processing precautions Pin function I/O port Port 0A Pin symbol Halt state P0A0 P0A1 The state before halt is held. (1) When set as output pins If externally pulled down while a high-level signal is being output, or if externally pulled up while a lowlevel signal is being output, the current drain increases. (2) When set as input pins (other than port 0B) When floating, noise, etc. increase the current drain. (3) Port 0B (P0B0 to P0B2) Since a pull-down resistor is built in, externally pulling the pin up causes the current drain to increase. The state existing prior to halt is held. Clock-stop state Pins are specified as general-purpose input ports. Pins P0A0 and P0A1 must be externally pulled down or pulled up to prevent the current drain from increasing. Port 0B (P0B0 to P0B2) is internally pulled down. Pins are specified as general-purpose input ports. The output contents are held. If externally pulled down while a highlevel signal is being output, or if externally pulled up while a low-level signal is being output, the current drain increases. Input port Port 0B P0B0 P0B1 P0B2 Output port Port 0A P0A2 P0A3 Port 0C P0C0 P0C1 P0C2 P0C3 Port 0D LCD segment P0D0/BEEP LCD0 | LCD8 VCOL VCOH EO Low level output (display off) PLL frequency synthesizer At PLL operation, the current drain increases. In the PLL disabled state, all pins enter floating status. When the level of the CE pin goes low, the PLL is automatically disabled. The supply current changes with the oscillation waveform of the crystal oscillation circuit. The larger the oscillation amplitude, the lower the supply current. Since the oscillation amplitude is governed by the crystal and load capacitor used, evaluation is necessary. PLL disabled state. All pins enter the floating state. Crystal oscillation circuit XIN XOUT The XIN pin is pulled down internally and the XOUT pin outputs high level. 88 PD17015 14.6 DEVICE OPERATION CONTROL BY THE CE PIN The CE pin controls the following functions by means of the input level and rising edge of a signal received from the outside: (1) PLL frequency synthesizer (2) Clock-stop instruction disable/enable (3) Device reset 14.6.1 PLL Frequency Synthesizer Operation Control The PLL frequency synthesizer can operate only when the CE pin is high level. When the level of the CE pin goes low, the PLL is automatically disabled. In PLL disabled state, the VCOH, VCOL, or EO pin enters the floating state. The PLL frequency synthesizer can be disabled by program even when the CE pin is high level. 14.6.2 Clock-Stop Instruction Disable/Enable Control The clock-stop instruction ("STOP s" instruction) is valid only when the CE pin is low level. If the CE pin is high level, the clock-stop instruction is executed as a no operation instruction (NOP). 14.6.3 Device Reset Reset (CE reset) can be applied to the device by raising the CE pin from low level to high level. Besides CE reset, there is also power-on reset, which is activated when VDD is turned on. For details, see Chapter 15. 89 PD17015 14.6.4 Signal Input to CE Pin To prevent erroneous operation by noise, the CE pin does not accept signals with a low or high level width of less than 140 s. The level of the signal input to the CE pin can be detected with the CE flag of the CE pin level judge register. Fig. 14-5 shows the relationship between input signal and CE flag. Fig. 14-5 Relationship of Signal Input to CE Pin and CE Flag CE pin CE flag H L 1 0 Less than 140 s 140 s Less than 140 s 140 s CE reset PLL operation enabled STOP s instruction invalid (NOP) PLL disabled STOP s instruction valid PLL disabled STOP s instruction invalid (NOP) CE reset is applied in synchronization with the next setting of the BTM0CY flag. 14.6.5 Organization and Functions of CE Pin Level Judge Register The CE pin level judge register monitors the CE pin input signal level. Its organization and functions are shown below. Fig. 14-6 Configuration of CE Pin Level Judge Register Flag symbol Register b3 CE pin level judge register 0 b2 0 b1 0 b0 C E 6AH R Address Read/write Detects the level input at the CE pin. 0 1 Low level input High level input Fixed to 0. Upon reset Power-on Clock stop CE 0 0 0 - - - The CE flag also does not change when the CE pin receives signals having a low or high level width of less than 140 s. 90 PD17015 15. RESET The reset function is used to initialize device operation. 15.1 OUTLINE OF RESET FUNCTION Fig. 15-1 outlines the reset block. To reset a device, apply one of the following methods, as necessary. 1 2 Power-on reset : Reset by applying supply voltage VDD CE reset : Reset with the CE pin Power-on reset is applied when VDD rises from a certain voltage. CE reset is applied when the level of the CE pin goes from low to high. The main differences between power-on reset and CE reset are the initial values of the peripheral control register and the operation of the power failure detection circuit, as described in Section 15.5. Power-on reset and CE reset are controlled by the reset signals (IRES, RES, or RESET signal) output from the reset control circuit shown in Fig. 15-1. Table 15-1 indicates the relationship between the internal reset signal and each reset. Fig. 15-1 Outline of the Reset Block Power failure detection block Timer block XIN BTM0CY flag read R STOP s instruction S Q Frequency divider XOUT Basic timer 0 Basic timer 0 carry disable flip-flop IRES Power-on clear signal (POC) Reset control circuit RES RESET Forced halt of release by BTM0CY flag Peripheral control register VDD Voltage detection circuit Rising edge detection circuit CE System register Stack Program counter STOP instruction Table 15-1 Relationship Between Internal Reset Signal and Each Reset Output signal Internal reset signal At CE reset x At poweron reset q At clock-stop Contents controlled by each reset signal IRES q Forces the device into the halt state. The halt state is released by the setting of the BTM0CY flag. Initializes some peripheral control registers. Initializes the program counter, stack, system register, and some peripheral control registers. RES RESET x q q q q q 91 PD17015 15.2 POWER-ON RESET Power-on reset is executed by raising VDD from a certain voltage (called the power-on clear voltage) or less. When VDD is less than the power-on clear voltage, the power-on clear signal (POC) is output from the voltage detection circuit shown in Fig. 15-1. When the power-on clear signal is output, the crystal oscillation circuit stops and the device stops operating. While the power-on clear signal is being output, the IRES, RES and RESET signals are output. When VDD exceeds the power-on clear voltage, the power-on clear signal is dropped and crystal oscillation starts. At the same time, the IRES, RES and RESET signals are also dropped. Since the IRES signal halts release by the BTM0CY flag, power-on reset is applied at the rising edge of the next BTM0CY flag setting signal. This operation is shown in Fig. 15-2. At power-on reset, the program counter, stack, system register and control registers are initialized when the poweron clear signal is output. For the initial values, see the relevant items. In the CPU operation and clock-stop state, the power-on clear voltage is 1.8 V (rated value). Caution The power-on clear voltage varies with the CPU operating temperature, as follows: TA = -10 to +50 C: 1.8 V TA = -20 to +50 C: 1.9 V Fig. 15-2 Power-On Reset Operation 3.0 V VDD CE L H XOUT BTM0CY flag set pulse Power-on clear signal IRES RES RESET L H L H L H L H L H L Normal operation Device operation stopped Halt state 125 ms Power-on reset Program starts from address 0 Power-on clear voltage 0V H Reset signal Power-on clear release Oscillation start 92 PD17015 15.2.1 Power-On Reset at CPU Operation Fig. 15-3 (a) shows power-on reset at normal operation. As shown in Fig. 15-3 (a), when the VDD drops below 1.8 V (TA = -10 to +50 C), the power-on clear signal is output and operation of the device stops regardless of the input level of the CE pin. When VDD then rises to 1.8 V or greater, after a 125 ms halt, the program starts from address 0000H. CPU operation refers to the state in which the clock-stop instruction is not used. The power-on clear voltage in the halt state set by the halt instruction is also 1.8 V like CPU operation. 15.2.2 Power-On Reset in Clock-Stop State Fig. 15-3 (b) shows power-on reset in the clock-stop state. As shown in Fig. 15-3 (b), when VDD drops below 1.8 V (TA = -10 to +50 C), the power-on clear signal is output and device operation stops. However, since the device is in the clock-stop state, its operation apparently does not change. When VDD rises to 1.8 V or greater, after a 125 ms halt, the program starts from address 0000H. 15.2.3 Power-On Reset When VDD Rises From 0 V Fig. 15-3 (c) shows power-on reset when VDD rises from 0 V. As shown in Fig. 15-3 (c), the power-on clear signal is being output while VDD is rising from 0 V to 1.8 V (TA = -10 to +50 C). When VDD rises above the power-on clear voltage, the crystal oscillation circuit starts and after a 125 ms halt, the program starts from address 0000H. 93 PD17015 Fig. 15-3 Power-On Reset and VDD (TA = -10 to +50 C) (a) During CPU operation (also in the halt state) 3.0 V VDD 0V H CE L H XOUT Power-on clear signal L H L Normal operation Device operation stopped 1.8 V Power-on clear voltage Halt state 125 ms Power-on reset Program starts from address 0 Power-on clear release Oscillation start (b) At clock-stop 3.0 V VDD 0V H CE L H XOUT Power-on clear signal L H L Normal operation Device operation stopped 1.8 V Power-on clear voltage Clock-stop Halt state 125 ms Power-on reset Program starts from address 0 STOP s instruction Power-on clear release Oscillation start (c) When VDD rises from 0 V 3.0 V VDD 0V H CE L H XOUT Power-on clear signal L H L Device operation stopped Halt state 125 ms Power-on clear release Power-on reset Oscillation start Program starts from address 0 1.8 V Power-on clear voltage 94 PD17015 15.3 CE RESET CE reset is executed by raising the CE pin from low level to high level. When the CE pin rises to high level, the RESET signal is output and the device is reset in synchronization with the rising edge of the pulse used for the next setting of the BTM0CY flag. When CE reset is applied, the RESET signal initializes the program counter, stack, system register, and some peripheral control registers to their initial value and executes the program from address 0000H. For the initial values, see the relevant item. CE reset operation is different when clock-stop is used and when it is not used. 15.3.1 CE Reset When Clock-Stop (STOP s Instruction) Not Used Fig. 15-4 shows the reset operation when clock-stop is not used. When clock-stop (STOP s instruction) is not used, the CE pin becomes high level. Then, RESET signal is output, and reset is applied at the rising edge of the selected pulse (125 ms) used for setting the BTM0CY flag. Fig. 15-4 CE Reset Operation When Clock-Stop Not Used 3.0 V VDD CE L H XOUT BTM0CY flag set pulse IRES RES RESET L H L H L H L H L Normal operation Normal operation 0V H Reset signal CE reset is applied at the rising edge of the pulse used for setting the BTM0CY flag. This period, t, varies with the timing when the CE pin signal rises. It falls in the range from 0 to 125 ms (0 < t < 125 ms), which is the selected set time of the BTM0CY flag. The program continues to run during this period. 95 PD17015 15.3.2 CE Reset When Clock-Stop (STOP s Instruction) Used Fig. 15-5 shows the reset operation when clock-stop is used. When clock-stop is used, the IRES, RES and RESET signals are output at the time the "STOP s" instruction is executed. Since the IRES signal is output continuously while the CE pin is low level, release by the BTM0CY flag is forcibly halted. Since the clock itself stops, the device stops operating. When the CE pin rises to high level, the clock-stop state is released and oscillation begins. The IRES signal halts release by the BTM0CY flag. When the pulse used for setting the BTM0CY flag rises after the CE pin rises, the halt state is released and the program starts from address 0. Fig. 15-5 CE Reset Operation When Clock-Stop Used 3.0 V VDD CE L H XOUT BTM0CY flag set pulse IRES RES RESET L H L H L H L H L Normal operation Clock-stop state Halt state 125 ms CE reset Program starts from address 0. 0V H Reset signal STOP s instruction Clock stop release Oscillation start 15.3.3 Cautions at CE Reset When CE reset is used, careful attention must be given to points (1) and (2) below regardless of the instruction being executed. (1) Time required for clock and other timer processing When writing a clock program by using basic timer 0 and basic timer 1 interrupts, the program must end processing within a certain time. For details, see Section 10.2.5. (2) Processing of data, flags, etc. used in the program Care must be exercised when rewriting the contents of data, flags, etc. that cannot be processed by one instruction so that the contents do not change even when CE reset is applied. Examples are given below: 96 PD17015 Example 1 R1 R2 R3 R4 M1 M2 START: Key-in processing R1 Contents of key A R2 Contents of key B SET2 SUB SUB SKT1 BR MAIN: Key-in processing R3 Contents of key C R4 Contents of key D ST ST ERROR: BR M1, R3 M2, R4 MAIN ;2 ;3 ; Security code rewrite mode ; Assigns the contents of the pressed keys to R3 ; and R4. ; Rewrites the security code. CMP, Z R1, M1 R2, M2 Z ERROR ; Detects that the input data does not match the ; security code. ;1 ; Security code input wait mode ; Assigns the contents of the pressed keys to R1 ; and R2 ; Compares the input data with the security code. MEM MEM MEM MEM MEM MEM 0.01H 0.02H 0.03H 0.04H 0.11H 0.12H ; First digit of security code keyed in ; Second digit of security code keyed in ; Data of the first digit when the security code is changed ; Data of the second digit when the security code is changed ; First digit of the current security code ; Second digit of the current security code Stops the operation. Suppose, in the program in example 1, that the security code is 12H. The contents of data memory M1 and M2 are 1H and 2H, respectively. When a CE reset occurs, the key input is compared with security code 12H in 1 . If they match, processing is performed. If the security code is changed as part of main processing, the new code is written to M1 and M2 in 2 and 3 . If the security code is changed to 34H, for example, 3H and 4H are written to M1 and M2 in 2 and 3 . If a CE reset occurs after 2 , the program starts from 0000H, without executing 3 . The security code is actually changed to 32H, making it impossible to remove the security lock. If this problem occurs, use a program like that shown in example 2 below: 97 PD17015 Example 2 R1 R2 R3 R4 M1 M2 CHANGE MEM MEM MEM MEM MEM MEM FLG 0.01H 0.02H 0.03H 0.04H 0.11H 0.12H 0.13H.0 ; First digit of security code keyed in ; Second digit of security code keyed in ; Data of the first digit when the security code is ; changed ; Data of the second digit when the security code is ; changed ; First digit of the current security code ; Second digit of the current security code ; The flag is set to 1 while the security code is being ; changed. START: Key-in processing R1 Contents of key A R2 Contents of key B SKT1 BR ST ST CLR1 SECURITY_CHK: SET2 SUB SUB SKT1 BR MAIN: Key-in processing R3 Contents of key C R4 Contents of key D SET1 ST ST CLR1 BR ERROR: Stops the operation. The program in example 2 sets the CHANGE flag in 5 to 1 before rewriting the security code in 2 and 3 . Even if a CE reset occurs before 3 , the data is written again in 4 ; Security code input wait mode ; Assigns the contents of the pressed keys to R1 ; and R2. ; If the CHANGE flag is set to 1 ; Writes the data to M1 and M2 again. CHANGE M1, R3 M2, R4 CHANGE CMP, Z R1, M1 R2, M2 Z ERROR ; 4 SECURITY_CHK :1 ; Compares the input data with the security code. ; Detects that the input data does not match the ; security code. ; Security code rewrite mode ; Assigns the contents of the pressed keys to R3 ; and R4. ; Holds the CHANGE flag to 1 until the changing of the ; security code is completed. ; Rewrites the security code. ; Sets the CHANGE flag to 0 once changing of the ; security code is completed. CHANGE M1, R3 M2, R4 CHANGE MAIN ;5 ;2 ; 3 . 98 PD17015 15.4 RELATIONSHIP BETWEEN CE RESET AND POWER-ON RESET When VDD is first turned on, power-on reset and CE reset may be applied simultaneously. Sections 15.4.1 through 15.4.3 describe this reset operation. 15.4.1 When VDD Pin and CE Pin Rise Simultaneously Fig. 15-6 (a) shows the reset operation. Power-on reset starts the program from address 0000H. 15.4.2 15.4.1. 15.4.3 When CE Pin Raised After Power-On Reset When CE Pin Raised in Forced Halt State Caused by Power-On Reset. Fig. 15-6 (b) shows the reset operation. Power-on reset starts the program from address 0000H, as in Section Fig. 15-6 (c) shows the reset operation. Power-on reset starts the program from address 0000H. CE reset restarts the program from address 0000H at the rising edge of the next BTM0CY flag setting signal. 99 PD17015 Fig. 15-6 Relationship Between Power-On Reset and CE Reset (TA = -10 to +50 C) (a) When VDD and CE pin raised simultaneously 3.0 V VDD 0V H CE L BTM0CY flag set pulse H L Operation stopped 1.8 V Power-on clear voltage Halt state 125 ms Normal operation Power-on reset Program start (b) When CE Pin Raised in Halt State 3.0 V VDD 0V H CE L BTM0CY flag set pulse H L Operation stopped 1.8 V Power-on clear voltage Halt state 125 ms Normal operation Power-on reset Program start (c) When CE Pin Raised After Power-On Reset 3.0 V VDD 0V H CE L BTM0CY flag set pulse H L Operation stopped 1.8 V Power-on clear voltage Halt state 125 ms Normal operation CE reset Program start Power-on reset Program start 100 PD17015 15.5 POWER FAILURE DETECTION Power failure detection is used to judge whether the device is reset by turning on VDD or by the CE pin, as shown in Fig. 15-7. Since the contents of the data memory, output ports, etc. become "undefined" when VDD is turned on, they are initialized by power failure detection. A power failure can be detected by using a power failure detection circuit to detect the BTM0CY flag. Fig. 15-7 Power Failure Detection Flowchart Program start Power failure detection Power failure No power failure Data memory, output port, etc. initialization 15.5.1 Power Failure Detection Circuit As shown in Fig. 15-1, the power failure detection circuit consists of a voltage detection circuit and timer carry disable flip-flop that is reset by the output (power-on clear signal) of the voltage detection circuit, and basic timer 0 carry. The basic timer 0 carry disable flip-flop is set (1) by the power-on clear signal and is cleared (0) when a BTM0CY flag read instruction is executed. When the basic timer 0 carry disable flip-flop is set (1), the BTM0CY flag is not set (1). That is, when the power-on clear signal is output (at power-on reset), the program starts in the state in which the BTM0CY flag is reset and the setting disabled state is set until a BTM0CY read instruction is executed thereafter. Once a BTM0CY read instruction is executed, the BTM0CY flag is set at each rising edge of the BTM0CY flag set pulse thereafter. When reset is applied to the device, the contents of the BTM0CY flag are monitored. If the BTM0CY flag has been cleared (0), power-on reset (power failure) is judged and if the BTM0CY flag has been set (1), CE reset (no power failure) is judged. Since the voltage that can detect a power failure is the same as the voltage applied by power-on reset, VDD becomes 1.8 V (TA = -10 to +50 C) at crystal oscillation and clock-stop (see Section 15.2). Fig. 15-8 shows the BTM0CY flag state transition. Fig. 15-9 shows timing chart and BTM0CY flag operation specified in Fig. 15-8. 101 PD17015 Fig. 15-8 BTM0CY Flag State Transition CE = low 1 CE = optional VDD = low Operation stopped CE = high VDD = L1.8 V 2 Crystal oscillation start Forced halt (approx. 125 ms) 3 BTM0CY flag setting disabled state 4 5 Power-on reset CE = L CE = H CE = HL 6 7 Clock-stop STOP 0 Normal operation Normal operation 8 BTM0CY = 0 CE reset Rising edge of BTM0CY flag set pulse CE = LH 9 Normal operation CE reset wait Crystal oscillation start Forced halt (125 ms) CE = LH 10 SKT1 BTM0CY or SKF1 BTM0CY 11 SKT1 BTM0CY or SKF1 BTM0CY 14 15 12 13 Clock-stop BTM0CY flag setting enable state STOP 0 Normal operation CE = HL Normal operation 16 BTM0CY = 1 CE reset Rising edge of BTM0CY flag set pulse CE = LH 17 Normal operation CE reset wait Crystal oscillation start Forced halt (125 ms) CE = LH 102 PD17015 Fig. 15-9 BTM0CY Flag Operation (a) When BTM0CY flag not detected even once (neither SKT1 BTM0CY nor SKF1 BTM0CY executed) 5 3.0V VDD 0V H CE L BTM0CY flag set pulse H L H BTM0CY L Fig. 15-8 operation 1 2 6 5 8 6 5 4 9 6 1 3 7 7 STOP 0000B (b) When power failure detected with BTM0CY flag 3.0V VDD 0V H CE L BTM0CY flag set pulse H L H BTM0CY L SKT1 instruction Fig. 15-8 operation 1 2 6 14 13 16 14 13 12 17 14 1 3 11 15 15 STOP 0000B BTM0CY=0 Power failure BTM0CY=1 No power failure BTM0CY=1 No power failure 103 PD17015 15.5.2 Cautions at Power Failure Detection with BTM0CY Flag When clock counting, etc. is performed with the BTM0CY flag, careful attention must be given to the following points. (1) Clock updating When writing a clock program by using basic timer 0, the clock must be updated after a power failure. This is because the BTM0CY flag is cleared (0) and one clock count is lost by BTM0CY flag reading when a power failure is detected. (2) Clock update processing time When the clock is updated, its processing must end before the next rising edge of the BTM0CY flag set pulse. This is because if the CE pin rises to high level during clock update processing, the clock update processing will not be executed up to the end and a CE reset will be applied. For (1) and (2) above, see Section 10.2.6 (1). When processing is performed at a power failure, careful attention must be given to the following point. (3) Power failure detection timing When clock counting, etc. is performed with the BTM0CY flag, the flag must be read for power-failure detection before the next rising edge of the BTM0CY flag set pulse, after a program starts from address 0000H. This is because when the BTM0CY flag set time is set to 125 ms, for instance, and power failure detection is performed 126 ms after the program starts, one BTM0CY flag is lost. See Section 10.2.6 (1). As shown in the example on the next page, power failure detection and initialization must be performed within the BTM0CY flag set time. This is because when the CE pin is raised and CE reset is applied during power failure processing and initialization, these processings are interrupted and a problem may occur. 104 PD17015 Example Sample program START: ;1 Reset processing ;2 SKT1 BR BACKUP: ;3 Clock updating BR INITIAL: ; 4 ; Program address 0000H BTM0CY INITIAL ; Power failure detection MAIN Initialization MAIN: Main process SKT1 BR BTM0CY MAIN Clock updating BR Operation example MAIN 3.0 V VDD 0V H CE L 500 ms H BTM0CY flag set pulse L 1 4 1 3 2 Power failure detection 2 Power failure detection When the processing time When the processing time of 1 + 3 is too long, a of 1 + 4 is 125 ms or longer, CE reset is applied. a CE reset is applied midway through processing 4 . CE reset CE reset 105 PD17015 16. INSTRUCTION SET 16.1 LIST OF INSTRUCTION SET b15 b14-b11 BIN 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 HEX 0 1 2 3 4 5 6 ADD SUB ADDC SUBC AND XOR OR RET RETSK GET PUT RORC STOP HALT NOP LD SKE MOV SKNE BR r, m r, m r, m r, m r, m r, m r, m ADD SUB ADDC SUBC AND XOR OR m, #n4 m, #n4 m, #n4 m, #n4 m, #n4 m, #n4 m, #n4 0 1 0 1 1 1 7 DBF, p p, DBF r s h 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 8 9 A B C D E F r, m m, #n4 @r, m m, #n4 addr ST SKGE MOV SKLT CALL MOV SKT SKF m, r m, #n4 m, @r m, #n4 addr m, #n4 m, #n m, #n 106 PD17015 16.2 INSTRUCTIONS Legend ASR addr CMP CY DBF h m mR mC n n4 PC p pH pL r s (x) : Address stack register pointed to by the stack pointer : Program memory address (11 bits) : Compare flag : Carry flag : Data buffer : Halt release condition : Data memory address specified by mR and mC : Data memory row address (high-order) : Data memory column address (low-order) : Bit position (four bits) : Immediate data (four bits) : Program counter : Peripheral address : Peripheral address (three high-order bits) : Peripheral address (four low-order bits) : General register column address : Stop release condition : Contents of x 107 PD17015 Instruction set Add Mnemonic ADD Instruction code Operand r, m m, #n4 ADDC r, m m, #n4 Subtract SUB r, m m, #n4 SUBC r, m m, #n4 Logical operation OR r, m m, #n4 AND r, m m, #n4 XOR r, m m, #n4 Test SKT SKF Compare SKE SKNE SKGE SKLT Rotation RORC m, #n m, #n m, #n4 m, #n4 m, #n4 m, #n4 r (r) (r) + (m) (m) (m) + n4 (r) (r) + (m) + CY (m) (m) + n4 + CY (r) (r) - (m) (m) (m) - n4 (r) (r) - (m) - CY (m) (m) - n4 - CY (r) (r) (m) (m) (m) n4 (r) (r) (m) (m) (m) n4 (r) (r) Operation Op code 00000 10000 00010 10010 00001 10001 00011 10011 00110 10110 00100 10100 00101 10101 11110 11111 01001 01011 11001 11011 00111 mR mR mR mR mR mR mR mR mR mR mR mR mR mR mR mR mR mR mR mR 000 Operand mC mC mC mC mC mC mC mC mC mC mC mC mC mC mC mC mC mC mC mC 0111 r n4 r n4 r n4 r n4 r n4 r n4 r n4 n n n4 n4 n4 n4 r (m) n4 (m) (m) CMP 0, if (m) n = n, then skip CMP 0, if (m) n = 0, then skip (m) - n4, skip if zero (m) - n4, skip if not zero (m) - n4, skip if not borrow (m) - n4, skip if borrow CY (r)b3 (r)b2 (r)b1 (r)b0 (r) (m) (m) (r) (mR, (r)) (m) (m) (mR, (r)) (m) n4 DBF (p) (p) DBF PC10-0 addr ASR PC, PC10-0 addr PC ASR PC ASR, and skip Transfer LD ST MOV r, m m, r @r, m m, @r m, #n4 01000 11000 01010 11010 11101 00111 00111 01100 11100 00111 00111 00111 00111 00111 mR mR mR mR mR pH pH mC mC mC mC mC 1011 1010 addr addr r r r r n4 pL pL GET PUT Branch Sub-routine BR CALL RET RETSK Others STOP HALT NOP DBF, p p, DBF addr addr 000 001 010 011 100 1110 1110 1111 1111 1111 0000 0000 s h 0000 s h STOP HALT No operation 108 PD17015 16.3 ASSEMBLER (AS17K) BUILT-IN MACRO INSTRUCTIONS Legend flag n <> : FLG-type symbol : An operand enclosed in < > is optional. Mnemonic Built-in macro SKTn SKFn SETn CLRn NOTn Operand flag 1, ... flag n flag 1, ... flag n flag 1, ... flag n flag 1, ... flag n flag 1, ... flag n Operation if (flag 1) to (flag n) = all "1", then skip if (flag 1) to (flag n) = all "0", then skip (flag 1) to (flag n) 1 (flag 1) to (flag n) 0 if (flag n) = "0", then (flag n ) 1 if (flag n) = "1", then (flag n) 0 if description = NOT flag n, then (flag n ) 0 if description = flag n, then (flag n) 1 n 1n4 1n4 1n4 1n4 1n4 INITFLG 1n4 109 PD17015 17. RESERVED SYMBOLS 17.1 SYSTEM REGISTER (SYSREG) Symbol AR3 AR2 AR1 AR0 WR BANK IXH MPH MPE IXM MPL IXL RPH RPL PSW BCD CMP CY Z IXE Attribute MEM MEM MEM MEM MEM MEM MEM MEM FLG MEM MEM MEM MEM MEM MEM FLG FLG FLG FLG FLG Value 0.74H 0.75H 0.76H 0.77H 0.78H 0.79H 0.7AH 0.7AH 0.7AH.3 0.7BH 0.7BH 0.7CH 0.7DH 0.7EH 0.7FH 0.7EH.0 0.7FH.3 0.7FH.2 0.7FH.1 0.7FH.0 Read/write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Bits 15 to 12 of the address register Bits 11 to 8 of the address register Bits 7 to 4 of the address register Bits 3 to 0 of the address register Window register Bank register Index register high Memory pointer high Memory pointer enable flag Index register middle Memory pointer low Index register low General register pointer high General register pointer low (Only low-order one bit is valid.) Program status word BCD flag Compare flag Carry flag Zero flag Index enable flag (Fixed to 0.) (Fixed to 0.) 17.2 DATA BUFFER (DBF) Symbol DBF3 DBF2 DBF1 DBF0 Attribute MEM MEM MEM MEM Value 0.0CH 0.0DH 0.0EH 0.0FH Read/write R/W R/W R/W R/W DBF bits 15 to 12 DBF bits 11 to 8 DBF bits 7 to 4 DBF bits 3 to 0 Description 110 PD17015 17.3 LCD SEGMENT REGISTER Symbol LCDD8 LCDD7 LCDD6 LCDD5 LCDD4 LCDD3 LCDD2 LCDD1 LCDD0 Attribute MEM MEM MEM MEM MEM MEM MEM MEM MEM Value 0.61H 0.62H 0.63H 0.64H 0.65H 0.66H 0.67H 0.68H 0.69H Read/write R/W R/W R/W R/W R/W R/W R/W R/W R/W LCD segment register LCD segment register LCD segment register LCD segment register LCD segment register LCD segment register LCD segment register LCD segment register LCD segment register Description 17.4 PORT REGISTER Symbol P0A3 P0A2 P0A1 P0A0 P0B2 P0B1 P0B0 P0C3 P0C2 P0C1 P0C0 P0D0 Attribute FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG Value 0.70H.3 0.70H.2 0.70H.1 0.70H.0 0.71H.2 0.71H.1 0.71H.0 0.72H.3 0.72H.2 0.72H.1 0.72H.0 0.73H.0 Read/write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit 3 of port 0A Bit 2 of port 0A Bit 1 of port 0A Bit 0 of port 0A Bit 2 of port 0B Bit 1 of port 0B Bit 0 of port 0B Bit 3 of port 0C Bit 2 of port 0C Bit 1 of port 0C Bit 0 of port 0C Bit 0 of port 0D Description 111 PD17015 17.5 PERIPHERAL CONTROL REGISTER Symbol LCDEN BEEP0SEL P0ABIO1 P0ABIO0 PLLMD1 PLLMD0 PLLRFCK1 PLLRFCK0 CE PLLUL BTM0CY BTM1CY Attribute FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG Value 0.6AH.3 0.6AH.2 0.6AH.1 0.6AH.0 0.6BH.3 0.6BH.2 0.6BH.1 0.6BH.0 0.6CH.0 0.6DH.0 0.6EH.0 0.6FH.0 Read/write R/W R/W R/W R/W R/W R/W R/W R/W R R R R LCD enable flag P0D0/BEEP pin selection flag P0A1 I/O selection flag P0A0 I/O selection flag PLL mode selection flag PLL mode selection flag Description PLL reference clock selection flag PLL reference clock selection flag CE pin status flag PLL unlock flip-flop flag Basic timer 0 carry flag Basic timer 1 carry flag 17.6 PERIPHERAL HARDWARE REGISTER Symbol PLLR Attribute DAT Value 41H Read/write R/W PLL data register Description 17.7 OTHERS Symbol DBF Attribute DAT Value 0FH Description Fixed operand value for a PUT/GET instruction 112 PD17015 18. ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS (TA = 25 C) 5 Parameter Supply voltage Input voltage Symbol VDD VI CE pin Conditions Rated value -0.3 to +4.0 -0.3 to VDD + 0.6 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 Unit V V V V mA mA mA mA C C Except for the CE pin Output voltage Output high current VO IOH Each pin Total for all pins Output low current IOL Each pin Total for all pins Operating ambient temperature Storage temperature TA -3.0 -20.0 3.0 20.0 -20 to +50 Tstg -55 to +125 Caution Absolute maximum ratings are rated values beyond which physical damage may be caused to the product; if any of the parameters in the table above exceeds its rated value, even momentarily, the quality of the product may deteriorate. Therefore, ensure that the product is used within the rated values. RECOMMENDED OPERATING RANGES (TA = -10 to +50 C) Parameter Supply voltage Symbol VDD1 VDD2 CPU operation Conditions Min. 1.8 1.9 Typ. 3.0 3.0 Max. 3.6 3.6 500 Unit V V ms CPU operation, TA = -20 to +50 C VDD: 0 1.8 V TA = -20 to +50 C Rise time of supply voltage trise 113 PD17015 DC CHARACTERISTICS (TA = -10 to +50 C, VDD = 1.8 to 3.6 V) Parameter Supply current Symbol IDD1 Conditions When the CPU and PLL are operating, with a sinusoidal wave applied to the XIN pin (fIN = 75 kHz, VIN = VDD) and VCOH pin (fIN = 220 MHz, VIN = 0.2 VP-P) When the CPU is operating but the PLL is not, with a sinusoidal wave applied to the XIN pin (fIN = 75 kHz, VIN = VDD) When the CPU is operating but the PLL is not (when the HALT instruction is issued), with a sinusoidal wave applied to the XIN pin (fIN = 75 kHz, VIN = VDD) When a power failure is detected with basic timer 0F/F When the crystal oscillation is stopped TA = 25 C, VDD = 3.0 V When the crystal oscillation is stopped VDD = 3.0 V Input high voltage VIH1 VIH2 Input low voltage VIL1 VIL2 Output high current IOH1 IOH2 IOH3 Output low current IOL1 IOL2 IOL3 IOL4 Input high current IIH1 IIH2 LCD drive voltage VLCD1 CE, P0A0, P0A1 P0B0-P0B2 CE, P0A0, P0A1 P0B0-P0B2 P0A0, P0A1, P0C0-P0C3, P0D0 VOH = VDD - 1 V EO LCD0-LCD8 P0A0, P0A1, P0D0 EO P0C0-P0C3 VOH = VDD - 1 V VOH = VLCD1 - 1 V VLCD1 = 2.7 to 3.3 V VOL = 1 V VOL = 1 V VOL = 1 V -0.2 -20 0.5 0.2 5 20 3 35 2.7 3.0 3.3 100 150 mA 0.8VDD 0.6VDD 0 0 -0.5 VDD VDD 0.2VDD 0.1VDD V V V V mA 1.8 Min. Typ. 9 Max. 16 Unit mA IDD2 30 70 A IDD3 15 30 A Data hold voltage Data hold current VDDR IDDR1 IDDR2 3.6 3 10 V A A A mA mA A A A A V LCD0-LCD8 VOL = 1 V, VLCD1 = 2.7 to 3.3 V When the P0B0 to P0B2 pins are pulled down When the XIN pin is pulled down VIH = VDD Output between LCD0 and LCD8 pins must be left open. Between VLCD0 and GND pins = 0.1 F, between VLCD1 and GND pins = 0.1 F, and between CAP0 and CAP1 pins = 0.01 F TA = 25 C EO Output-off leakage current IL 1 A AC CHARACTERISTICS (TA = -10 to +50 C, VDD = 1.8 to 3.6 V) Parameter Operating frequency Symbol fIN1 Conditions VCOL MF mode, with a sinusoidal wave applied at VIN = 0.2 Vp-p VCOL HF mode, with a sinusoidal wave applied at VIN = 0.2 Vp-p VCOH VHF mode, with a sinusoidal wave applied at VIN = 0.2 Vp-p Min. 0.5 Typ. Max. 8 Unit MHz fIN2 6 55 MHz fIN3 40 220 MHz 114 PD17015 19. PACKAGE DRAWING 38 PIN PLASTIC SHRINK SOP (300 mil) 38 20 detail of lead end 1 A 19 H G I 3 +7 -3 F J E N C D MM B K L P38GS-65-300B-1 NOTE Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition. ITEM A B C D E F G H I J K L M N MILLIMETERS 12.71 MAX. 0.51 MAX. 0.65 (T.P.) 0.30 0.10 0.125 0.075 2.0 MAX. 1.7 0.1 8.1 0.3 6.1 0.2 1.0 0.2 0.15+0.10 -0.05 0.5 0.2 0.10 0.10 INCHES 0.501 MAX. 0.020 MAX. 0.026 (T.P.) 0.012+0.004 -0.005 0.005 0.003 0.079 MAX. 0.067 0.004 0.319 0.012 0.240 0.008 0.039+0.009 -0.008 0.006+0.004 -0.002 0.020+0.008 -0.009 0.004 0.004 115 PD17015 5 20. RECOMMENDED SOLDERING CONDITIONS The conditions listed below shall be met when soldering the PD17015. For details of the recommended soldering conditions, refer to our document SMD Surface Mount Technology Manual (IEI-1207). Please consult with our sales offices in case any other soldering process is used, or in case soldering is done under different conditions. Table 20-1 Soldering Conditions for Surface-Mount Devices PD17015GS-xxx-GJG: 38-pin plastic shrink SOP (300 mil) Soldering process Infrared ray reflow Soldering conditions Peak package's surface temperature: 235 C Reflow time: 30 seconds or less (at 210 C or more) Maximum allowable number of reflow processes: 2 Symbol IR35-00-2 VPS VP15-00-2 Wave soldering WS60-00-1 Partial heating method -- Caution Do not apply more than a single process at once, except for "Partial heating method." 116 PD17015 APPENDIX DEVELOPMENT TOOLS The following support tools are available for developing programs for the PD17015. Hardware Name In-circuit emulator IE-17K IE-17K-ETNote 1 EMU-17KNote 2 Description The IE-17K, IE-17K-ET, and EMU-17K are in-circuit emulators applicable to the 17K series. The IE-17K and IE-17K-ET are connected to the PC-9800 series (host machine) or IBM PC/ATTM through the RS-232-C interface. The EMU-17K is inserted into the extension slot of the PC-9800 series (host machine). Use the system evaluation board (SE board) corresponding to each product together with one of these in-circuit emulators. SIMPLEHOST TM , a man machine interface, implements an advanced debug environment. The EMU-17K also enables user to check the contents of the data memory in real time. The SE-17015 is an SE board for the PD17015. It is used solely for evaluating the system. It is also used for debugging in combination with the in-circuit emulator. The EP-17K38GT is an emulation probe for the PD17015GS. It is used to connect the SE board with the target system in combination with the EV9500GT-38. The EV-9500GT-38 is a flexible printed circuit board used for a 38-pin plastic shrink SOP (300 mil). This board is used to connect the EP-17K38GT to the target system. SE board (SE-17015) Emulation probe (EP-17K38GT) 5 5 Flexible printed circuit board for conversion (EV-9500GT-38Note 3) 5 Notes 1. Low-end model, operating on an external power supply 2. The EMU-17K is a product of IC Co., Ltd. Contact IC Co., Ltd. (Tokyo, 03-3447-3793) for details. 3. The EP-17K38GT is supplied together with two EV-9500GT-38s. A set of five EV-9500GT-38s is also available. 117 PD17015 Software Host machine PC-9800 series Distribution media 5.25-inch, 2HD 3.5-inch, 2HD IBM PC/AT 5.25-inch, 2HC 3.5-inch, 2HC Device file (AS17015) AS17015 is a device file for the PD17015. It is used together with the assembler (AS17K), which is applicable to the 17K series. PC-9800 series MS-DOS 5.25-inch, 2HD 3.5-inch, 2HD 5.25-inch, 2HC 3.5-inch, 2HC Support software (SIMPLEHOST) Name 17K series assembler (AS17K) Description AS17K is an assembler applicable to the 17K series. In developing PD17015 programs, AS17K is used in combination with a device file (AS17015). OS Part number S5A10AS17K S5A13AS17K S7B10AS17K S7B13AS17K S5A10AS17015 S5A13AS17015 S7B10AS17015 S7B13AS17015 S5A10IE17K S5A13IE17K S7B10IE17K S7B13IE17K MS-DOS TM PC DOS TM 5 IBM PC/AT PC DOS SIMPLEHOST, running on the WindowsTM, provides manmachine-interface in developing programs by using a personal computer and the incircuit emulator. PC-9800 MS-DOS series Windows 5.25-inch, 2HD 3.5-inch, 2HD IBM PC/AT PC DOS 5.25-inch, 2HC 3.5-inch, 2HC Remark The following table lists the versions of the operating systems described in the above table. OS MS-DOS PC DOS Windows Versions Ver. 3.30 to Ver. 5.00ANote Ver. 3.1 to Ver. 5.0Note Ver. 3.0 to Ver. 3.1 Note MS-DOS versions 5.00 and 5.00A and PC DOS Ver. 5.0 are provided with a task swap function. This function, however, cannot be used in these software packages. 118 PD17015 Cautions on CMOS Devices 1 Countermeasures against static electricity for all MOSs Caution When handling MOS devices, take care so that they are not electrostatically charged. Strong static electricity may cause dielectric breakdown in gates. When transporting or storing MOS devices, use conductive trays, magazine cases, shock absorbers, or metal cases that NEC uses for packaging and shipping. Be sure to ground MOS devices during assembling. Do not allow MOS devices to stand on plastic plates or do not touch pins. Also handle boards on which MOS devices are mounted in the same way. CMOS-specific handling of unused input pins Caution Hold CMOS devices at a fixed input level. Unlike bipolar or NMOS devices, if a CMOS device is operated with no input, an intermediatelevel input may be caused by noise. This allows current to flow in the CMOS device, resulting in a malfunction. Use a pull-up or pull-down resistor to hold a fixed input level. Since unused pins may function as output pins at unexpected times, each unused pin should be separately connected to the VDD or GND pin through a resistor. If handling of unused pins is documented, follow the instructions in the document. Statuses of all MOS devices at initialization Caution The initial status of a MOS device is unpredictable when power is turned on. Since characteristics of a MOS device are determined by the amount of ions implanted in molecules, the initial status cannot be determined in the manufacture process. NEC has no responsibility for the output statuses of pins, input and output settings, and the contents of registers at power on. However, NEC assures operation after reset and items for mode setting if they are defined. When you turn on a device having a reset function, be sure to reset the device first. 2 3 119 PD17051 [MEMO] SIMPLEHOST is a trademark of NEC Corporation. PC/AT and PC DOS are trademarks of IBM Corporation. MS-DOS and Windows are trademarks of Microsoft Corporation. The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customer must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices in "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact NEC Sales Representative in advance. Anti-radioactive design is not implemented in this product. M4 94.11 |
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